X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=debug%2Ftargets%2FSiFive%2FHiFive1.cfg;h=333c82e4706dd1eca8393180ca731ffe6dd7276b;hp=8f21b4776cb5728e65a8d05cf432b98a5932afbc;hb=4ab18e0f8e6381f0a16e8b812d4ee202e9465192;hpb=45380af7d42ee3302fc229030694f8ea4506d79f

diff --git a/debug/targets/SiFive/HiFive1.cfg b/debug/targets/SiFive/HiFive1.cfg
index 8f21b47..333c82e 100644
--- a/debug/targets/SiFive/HiFive1.cfg
+++ b/debug/targets/SiFive/HiFive1.cfg
@@ -17,6 +17,9 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1
 #-rtos riscv
 
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
 # Expose an unimplemented CSR so we can test non-existent register access
 # behavior.
 riscv expose_csrs 2288