From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 31 Oct 2018 02:21:53 +0000 (+0000)
Subject: working towards sv fp elwidth
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=054f9bcf0a15c6657006052de2ff9b52c3ed64f7

working towards sv fp elwidth
---

diff --git a/isa/rv64uf/sv_fadd_elwidth.S b/isa/rv64uf/sv_fadd_elwidth.S
index 9b5bc0d..264708a 100644
--- a/isa/rv64uf/sv_fadd_elwidth.S
+++ b/isa/rv64uf/sv_fadd_elwidth.S
@@ -3,6 +3,27 @@
 
 RVTEST_RV64UF
 
+#define SV_ELWIDTH_TEST( vl, wid1, wid2, wid3, testdata, answer ) \
+                                                                \
+        SV_FLW_DATA( f4, ( testdata + 0) , 0) ;                      \
+        SV_FLW_DATA( f5, ( testdata + 4), 0)  ;                      \
+        SV_FLW_DATA( f6, ( testdata + 8), 0)  ;                      \
+        SV_FLW_DATA( f7, ( testdata + 12), 0) ;                      \
+                                                                \
+        SET_SV_MVL( vl )                      ;                    \
+        SET_SV_3CSRS( SV_REG_CSR(0, 2, wid1, 2, 1),                \
+                      SV_REG_CSR(0, 4, wid2, 4, 1),                \
+                      SV_REG_CSR(0, 6, wid3, 6, 1) ) ;             \
+        SET_SV_VL( vl ) ;                                          \
+                                                                \
+        fadd.s f2, f4, f6;                                      \
+                                                                \
+        CLR_SV_CSRS() ;                                         \
+        SET_SV_VL(1) ;                                          \
+        SET_SV_MVL(1) ;                                         \
+                                                                \
+        TEST_SV_FW(0, f2, answer+0, 0) ;                        \
+        TEST_SV_FW(0, f3, answer+4, 0)
 
 # SV test: vector-vector fadd
 #
@@ -12,25 +33,8 @@ RVTEST_RV64UF
 # Test code region.
 RVTEST_CODE_BEGIN   # Start of test code.
 
-        SV_FLW_DATA( f4, testdata+0 , 0)
-        SV_FLW_DATA( f5, testdata+4, 0)
-        SV_FLW_DATA( f6, testdata+8, 0)
-        SV_FLW_DATA( f7, testdata+12, 0)
-
-        SET_SV_MVL(2)
-        SET_SV_3CSRS( SV_REG_CSR(0, 2, 2, 2, 1),
-                      SV_REG_CSR(0, 4, 0, 4, 1),
-                      SV_REG_CSR(0, 6, 0, 6, 1) )
-        SET_SV_VL(2)
-
-        fadd.s f2, f4, f6;
-
-        CLR_SV_CSRS()
-        SET_SV_VL(1)
-        SET_SV_MVL(1)
-
-        TEST_SV_FW(0, f2, answer+0, 0) 
-        TEST_SV_FW(0, f3, answer+4, 0) 
+        SV_ELWIDTH_TEST( 2, 2, 0, 0, testdata, answer );
+        SV_ELWIDTH_TEST( 2, 2, 2, 0, testdata2, answer2 );
 
         RVTEST_PASS           # Signal success.
 fail:
@@ -47,9 +51,18 @@ testdata:
         .float 1.0
         .float 2.0
 answer:
+        .word 0xffff5140   # 42.0 fp16
+        .word 0xffff5180   # 44.0 fp16
+
+
+testdata2:
+        .word 0xffff5120   # 41 fp16
+        .word 0xffff5140   # 42 fp16
+        .float 1.0
+        .float 2.0
+answer2:
         .word 0xffff5140
         .word 0xffff5180
-
 # Output data section.
 RVTEST_DATA_BEGIN   # Start of test output data region.
         .align 3