From: Tim Newsome <tim@sifive.com>
Date: Thu, 6 Jul 2017 22:09:09 +0000 (-0700)
Subject: Merge pull request #58 from riscv/fpga_reset_halt
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=14dfde33927bead9d08409e2d2b70c8bf5023095

Merge pull request #58 from riscv/fpga_reset_halt

debug: Make the 'out of reset' tests apply reset
---

14dfde33927bead9d08409e2d2b70c8bf5023095