From: Daniel Benusovich Date: Mon, 10 Dec 2018 06:25:53 +0000 (-0800) Subject: Correcting loading convention in load macro X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=1cbf167dd4cb9ba10b4c8517285c5e09d7e56692 Correcting loading convention in load macro --- diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h index 9f16a84..2242235 100644 --- a/isa/macros/simplev/sv_test_macros.h +++ b/isa/macros/simplev/sv_test_macros.h @@ -111,12 +111,12 @@ // Loads the source registers using load_instruction from testdata with a spacing of elwidth #define SV_LOAD_FORMAT(load_instruction, testdata, elwidth) \ - load_instruction( x12, testdata); \ - load_instruction( x13, testdata+elwidth); \ - load_instruction( x14, testdata+elwidth*2); \ - load_instruction( x15, testdata+elwidth*3); \ - load_instruction( x16, testdata+elwidth*4); \ - load_instruction( x17, testdata+elwidth*5); \ + load_instruction x12, (testdata); \ + load_instruction x13, (testdata+elwidth); \ + load_instruction x14, (testdata+elwidth*2); \ + load_instruction x15, (testdata+elwidth*3); \ + load_instruction x16, (testdata+elwidth*4); \ + load_instruction x17, (testdata+elwidth*5); \ // Loads the source registers using load_instruction from testdata with a spacing of elwidth and offset #define SV_LOAD_FORMAT_OFFSET(load_instruction, testdata, elwidth, offset) \ @@ -145,7 +145,7 @@ \ SV_ELWIDTH_TEST_INNER(SV_LOAD_FORMAT(load_instruction, testdata, elwidth), \ vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \ - expect1, expect2, expect3, code x28, x15, x12) \ + expect1, expect2, expect3, code x28, 0(x12)) \ // This should not be accessed directly. It is meant to be called through higher level macros. // If used: