From: Luke Kenneth Casson Leighton Date: Tue, 9 Oct 2018 10:40:16 +0000 (+0100) Subject: alter unit tests to match change in CSR table format X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=1e383ad459ac835bda65f03881443d78a1fa7444 alter unit tests to match change in CSR table format --- diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h index ddf951a..b3b06c0 100644 --- a/isa/macros/simplev/sv_test_macros.h +++ b/isa/macros/simplev/sv_test_macros.h @@ -1,15 +1,14 @@ -#define SV_REG_CSR( type, regkey, elwidth, regidx, isvec, packed ) \ - (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<14) | (packed<<15)) +#define SV_REG_CSR(type, regkey, elwidth, regidx, isvec) \ + (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<15)) +#define SV_PRED_CSR(type, regkey, zero, inv, regidx, packed) \ + (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (packed<<15)) -#define SV_PRED_CSR( type, regkey, zero, inv, regidx, active ) \ - (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (active<<14)) - -#define SET_SV_CSR( type, regkey, elwidth, regidx, isvec, packed ) \ - li x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec, packed ); \ +#define SET_SV_CSR( type, regkey, elwidth, regidx, isvec) \ + li x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \ csrrw x0, 0x4c0, x1 -#define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, active ) \ - li x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, active ); \ +#define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ) \ + li x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ); \ csrrw x0, 0x4c8, x1 #define SET_SV_2CSRS( c1, c2 ) \ diff --git a/isa/rv64uc/sv_c_lwsp.S b/isa/rv64uc/sv_c_lwsp.S index d643594..e30d11a 100644 --- a/isa/rv64uc/sv_c_lwsp.S +++ b/isa/rv64uc/sv_c_lwsp.S @@ -22,8 +22,8 @@ RVTEST_CODE_BEGIN li a4, 0 SET_SV_MVL(3) - SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1, 0), - SV_REG_CSR(1, 2, 0, 2, 1, 0) ) + SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1), + SV_REG_CSR(1, 2, 0, 2, 1) ) SET_SV_VL(3) mv a1, sp diff --git a/isa/rv64uc/sv_c_lwsp_predication.S b/isa/rv64uc/sv_c_lwsp_predication.S index d2caf8b..a0a2934 100644 --- a/isa/rv64uc/sv_c_lwsp_predication.S +++ b/isa/rv64uc/sv_c_lwsp_predication.S @@ -28,11 +28,11 @@ RVTEST_CODE_BEGIN la sp, data; SET_SV_MVL(3) - SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1, 0), - SV_REG_CSR(1, 2, 0, 2, 1, 0) ) + SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1), + SV_REG_CSR(1, 2, 0, 2, 1) ) SET_SV_2PREDCSRS( - SV_PRED_CSR(1, 2, 0, 0, 10, 1), - SV_PRED_CSR(1, 12, 0, 0, 11, 1) ); + SV_PRED_CSR(1, 2, 0, 0, 10, 0), + SV_PRED_CSR(1, 12, 0, 0, 11, 0) ); SET_SV_VL(3) diff --git a/isa/rv64uc/sv_c_mv.S b/isa/rv64uc/sv_c_mv.S index c85108c..11a042b 100644 --- a/isa/rv64uc/sv_c_mv.S +++ b/isa/rv64uc/sv_c_mv.S @@ -23,8 +23,8 @@ RVTEST_CODE_BEGIN # Start of test code. li x5, 0 # deliberately set x4 to 0 SET_SV_MVL(3) - SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1, 0), - SV_REG_CSR(1, 6, 0, 6, 1, 0) ) + SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1), + SV_REG_CSR(1, 6, 0, 6, 1) ) SET_SV_VL(3) .option rvc diff --git a/isa/rv64uc/sv_c_mv_predication.S b/isa/rv64uc/sv_c_mv_predication.S index 3ad6535..fc0bb74 100644 --- a/isa/rv64uc/sv_c_mv_predication.S +++ b/isa/rv64uc/sv_c_mv_predication.S @@ -17,11 +17,11 @@ RVTEST_RV64U # Define TVM used by program. li a4, pred2; \ \ SET_SV_MVL(3); \ - SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1, 0), \ - SV_REG_CSR(1, 6, 0, 6, 1, 0) ); \ + SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1), \ + SV_REG_CSR(1, 6, 0, 6, 1) ); \ SET_SV_2PREDCSRS( \ - SV_PRED_CSR(1, 3, 0, 0, 13, 1), \ - SV_PRED_CSR(1, 6, 0, 0, 14, 1) );\ + SV_PRED_CSR(1, 3, 0, 0, 13, 0), \ + SV_PRED_CSR(1, 6, 0, 0, 14, 0) );\ SET_SV_VL(3); \ \ .option rvc; \ diff --git a/isa/rv64uc/sv_c_swsp.S b/isa/rv64uc/sv_c_swsp.S index c29a9b4..7990707 100644 --- a/isa/rv64uc/sv_c_swsp.S +++ b/isa/rv64uc/sv_c_swsp.S @@ -22,8 +22,8 @@ RVTEST_CODE_BEGIN li a4, 1004; SET_SV_MVL(3) - SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1, 0), - SV_REG_CSR(1, 2, 0, 2, 1, 0) ) + SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1), + SV_REG_CSR(1, 2, 0, 2, 1) ) SET_SV_VL(3) mv a1, sp diff --git a/isa/rv64ud/sv_fadd.S b/isa/rv64ud/sv_fadd.S index 9ef2082..9057dff 100644 --- a/isa/rv64ud/sv_fadd.S +++ b/isa/rv64ud/sv_fadd.S @@ -22,8 +22,8 @@ RVTEST_CODE_BEGIN # Start of test code. SV_FLD_DATA( f8, testdata+56, 0) SET_SV_MVL(2) - SET_SV_2CSRS( SV_REG_CSR(0, 2, 0, 2, 1, 0), - SV_REG_CSR(0, 6, 0, 6, 1, 0) ) + SET_SV_2CSRS( SV_REG_CSR(0, 2, 0, 2, 1), + SV_REG_CSR(0, 6, 0, 6, 1) ) SET_SV_VL(2) fadd.d f2, f2, f6; diff --git a/isa/rv64ui/Makefrag.sv b/isa/rv64ui/Makefrag.sv index da91e06..ab4744d 100644 --- a/isa/rv64ui/Makefrag.sv +++ b/isa/rv64ui/Makefrag.sv @@ -8,6 +8,7 @@ rv64ui_sv_tests = \ sv_addi_scalar_src \ sv_addi_vector_vector \ sv_addi_predicated \ + sv_beq \ rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sv_tests)) rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sv_tests)) diff --git a/isa/rv64ui/sv_addi.S b/isa/rv64ui/sv_addi.S index 123052c..b73db85 100644 --- a/isa/rv64ui/sv_addi.S +++ b/isa/rv64ui/sv_addi.S @@ -18,7 +18,7 @@ RVTEST_CODE_BEGIN # Start of test code. SV_LD_DATA( x5, testdata+24, 0) SET_SV_MVL(2) - SET_SV_CSR(1, 3, 0, 3, 1, 0) + SET_SV_CSR(1, 3, 0, 3, 1) SET_SV_VL(2) addi x3, x3, 1 diff --git a/isa/rv64ui/sv_addi_predicated.S b/isa/rv64ui/sv_addi_predicated.S index 32902f0..46246ea 100644 --- a/isa/rv64ui/sv_addi_predicated.S +++ b/isa/rv64ui/sv_addi_predicated.S @@ -13,8 +13,8 @@ RVTEST_RV64U # Define TVM used by program. li x6, pred; \ \ SET_SV_MVL( 2); \ - SET_SV_CSR( 1, 3, 0, 3, 1, 0); \ - SET_SV_PRED_CSR( 1, 3, zero, inv, 6, 1); \ + SET_SV_CSR( 1, 3, 0, 3, 1); \ + SET_SV_PRED_CSR( 1, 3, zero, inv, 6, 0); \ SET_SV_VL( 2); \ \ addi x3, x3, 1; \ diff --git a/isa/rv64ui/sv_addi_redirect.S b/isa/rv64ui/sv_addi_redirect.S index 61e9284..74d41e0 100644 --- a/isa/rv64ui/sv_addi_redirect.S +++ b/isa/rv64ui/sv_addi_redirect.S @@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN # Start of test code. SV_LD_DATA( x5, testdata+24, 0) SET_SV_MVL(2) - SET_SV_CSR(1, 16, 0, 3, 1, 0) + SET_SV_CSR(1, 16, 0, 3, 1) SET_SV_VL(2) addi x16, x16, 1 diff --git a/isa/rv64ui/sv_addi_scalar_src.S b/isa/rv64ui/sv_addi_scalar_src.S index 182b2ae..e17df23 100644 --- a/isa/rv64ui/sv_addi_scalar_src.S +++ b/isa/rv64ui/sv_addi_scalar_src.S @@ -21,7 +21,7 @@ RVTEST_CODE_BEGIN # Start of test code. li x6, 41 # going to be stored in x3 *and* x4 (plus one, on each) SET_SV_MVL(2) - SET_SV_CSR(1, 3, 0, 3, 1, 0) + SET_SV_CSR(1, 3, 0, 3, 1) SET_SV_VL(2) addi x3, x6, 1 # x3 = x6+1 *AND* x4 = x6+1 diff --git a/isa/rv64ui/sv_addi_vector_vector.S b/isa/rv64ui/sv_addi_vector_vector.S index ea1f3c6..8594ba7 100644 --- a/isa/rv64ui/sv_addi_vector_vector.S +++ b/isa/rv64ui/sv_addi_vector_vector.S @@ -21,8 +21,8 @@ RVTEST_CODE_BEGIN # Start of test code. li x4, 0 # deliberately set x4 to 0 SET_SV_MVL(2) - SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1, 0), - SV_REG_CSR(1, 6, 0, 6, 1, 0) ) + SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1), + SV_REG_CSR(1, 6, 0, 6, 1) ) SET_SV_VL(2) addi x3, x6, 1