From: Luke Kenneth Casson Leighton Date: Thu, 1 Nov 2018 12:19:58 +0000 (+0000) Subject: add 32-16 fld unit test X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=2f2b767e8d3a4f975083dfb0ad9df58950c06948 add 32-16 fld unit test --- diff --git a/isa/rv64uf/sv_fld_elwidth.S b/isa/rv64uf/sv_fld_elwidth.S index 85f5987..17fab73 100644 --- a/isa/rv64uf/sv_fld_elwidth.S +++ b/isa/rv64uf/sv_fld_elwidth.S @@ -29,9 +29,9 @@ RVTEST_RV64UF # Define TVM used by program. SET_SV_VL( 1); \ SET_SV_MVL( 1); \ \ - TEST_SV_FW(0, f28, ans, 0); \ - TEST_SV_FW(0, f29, ans, 8); \ - TEST_SV_FW(0, f30, ans, 16); + TEST_SV_FD(0, f28, ans, 0); \ + TEST_SV_FD(0, f29, ans, 8); \ + TEST_SV_FD(0, f30, ans, 16); # SV test: vector-vector add # @@ -45,6 +45,7 @@ RVTEST_CODE_BEGIN # Start of test code. SV_ELWIDTH_TEST( fld , 3, 8, SV_W_DFLT, SV_W_DFLT, testdata1, answer2 ) SV_ELWIDTH_TEST( fld , 3, 8, SV_W_16BIT, SV_W_DFLT, testdata3, answer3) SV_ELWIDTH_TEST( fld , 5, 8, SV_W_16BIT, SV_W_32BIT, testdata3, answer4) + SV_ELWIDTH_TEST( fld , 3, 8, SV_W_32BIT, SV_W_16BIT, testdata4, answer5) /* SV_ELWIDTH_TEST( ld , 5, 8, SV_W_32BIT, SV_W_16BIT, testdata1, 0x6757271769592919, 0xa5a5a5a5a5a52616, 0xa5a5a5a5a5a5a5a5 ) @@ -99,11 +100,25 @@ answer4: .float 42.0 .float 44.0 + .float 1.0 + .float 1000.0 .float -1152.0 + .word 0xa5a5a5a5 + +testdata4: + + .float 42.0 + .float 44.0 .float 1.0 - .dword 0x00000000a5a5a5a5 .float 1000.0 - .float 0.0 + .float -1152.0 + .word 0xa5a5a5a5 + +answer5: + + .dword 0xa5a53c0051805140 + .dword 0xa5a5a5a5a5a5a5a5 + .dword 0xa5a5a5a5a5a5a5a5 # Output data section. RVTEST_DATA_BEGIN # Start of test output data region.