From: Tim Newsome <tim@sifive.com>
Date: Tue, 24 Oct 2017 18:55:01 +0000 (-0700)
Subject: Increase dual-core RV64 timeouts.
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=3d284202d1440fe7aa029fa667aec9d45b4c4892

Increase dual-core RV64 timeouts.

I need this for CompareSections to pass when I instrument spike to be
really slow.
---

diff --git a/debug/targets/RISC-V/spike64-2-rtos.py b/debug/targets/RISC-V/spike64-2-rtos.py
index d65d2ab..7e3fc7e 100644
--- a/debug/targets/RISC-V/spike64-2-rtos.py
+++ b/debug/targets/RISC-V/spike64-2-rtos.py
@@ -6,7 +6,7 @@ import spike64  # pylint: disable=import-error
 class spike64_2_rtos(targets.Target):
     harts = [spike64.spike64_hart(), spike64.spike64_hart()]
     openocd_config_path = "spike-rtos.cfg"
-    timeout_sec = 30
+    timeout_sec = 60
 
     def create(self):
         return testlib.Spike(self)
diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py
index 709ebbe..79aab3e 100644
--- a/debug/targets/RISC-V/spike64-2.py
+++ b/debug/targets/RISC-V/spike64-2.py
@@ -6,7 +6,7 @@ import spike64  # pylint: disable=import-error
 class spike64_2(targets.Target):
     harts = [spike64.spike64_hart(), spike64.spike64_hart()]
     openocd_config_path = "spike-2.cfg"
-    timeout_sec = 30
+    timeout_sec = 60
 
     def create(self):
         return testlib.Spike(self)