From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 2 Oct 2018 11:22:33 +0000 (+0100)
Subject: actually sv vector-vector add worked fine
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=4565d419df10f75233b58743b999b929fe133f16

actually sv vector-vector add worked fine

(forgot to set CSR on 2nd register)
---

diff --git a/isa/rv64ud/sv_fadd.S b/isa/rv64ud/sv_fadd.S
index f456119..9ef2082 100644
--- a/isa/rv64ud/sv_fadd.S
+++ b/isa/rv64ud/sv_fadd.S
@@ -22,7 +22,8 @@ RVTEST_CODE_BEGIN   # Start of test code.
         SV_FLD_DATA( f8, testdata+56, 0)
 
         SET_SV_MVL(2)
-        SET_SV_CSR(0, 2, 0, 2, 1, 0)
+        SET_SV_2CSRS( SV_REG_CSR(0, 2, 0, 2, 1, 0),
+                      SV_REG_CSR(0, 6, 0, 6, 1, 0) )
         SET_SV_VL(2)
 
         fadd.d f2, f2, f6;