From: Megan Wachs <megan@sifive.com>
Date: Mon, 15 May 2017 07:54:41 +0000 (-0700)
Subject: debug: Use consistent 'sim_cmd' argument.
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=46fdf4920da71f3f8690349d72fe6a516fd97735

debug: Use consistent 'sim_cmd' argument.
---

diff --git a/debug/targets.py b/debug/targets.py
index a69f43d..17e752d 100644
--- a/debug/targets.py
+++ b/debug/targets.py
@@ -127,7 +127,7 @@ class FreedomU500SimTarget(Target):
     openocd_config = "targets/%s/openocd.cfg" % name
 
     def target(self):
-        return testlib.VcsSim(simv=self.sim_cmd, debug=False)
+        return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
 
 targets = [
         Spike32Target,
diff --git a/debug/testlib.py b/debug/testlib.py
index a66d59a..df976df 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -113,7 +113,7 @@ class Spike(object):
 class VcsSim(object):
     def __init__(self, sim_cmd=None, debug=False):
         if sim_cmd:
-            cmd = shlex.split(simv)
+            cmd = shlex.split(sim_cmd)
         else:
             cmd = ["simv"]
         cmd += ["+jtag_vpi_enable"]