From: Megan Wachs <megan@sifive.com>
Date: Thu, 18 May 2017 19:14:07 +0000 (-0700)
Subject: Merge pull request #52 from riscv/vcs_sim_cmd
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=5ff7b723976b3736daa0f0ad5df71d40576a674a

Merge pull request #52 from riscv/vcs_sim_cmd

debug: Correct the calling for a 32-bit simulation target
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5ff7b723976b3736daa0f0ad5df71d40576a674a