From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 29 Oct 2018 08:10:13 +0000 (+0000)
Subject: add sv store elementwidth test
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=64055011fa3e7bd519a98c6abd39588fe24cc2ad

add sv store elementwidth test
---

diff --git a/isa/rv64ui/Makefrag.sv b/isa/rv64ui/Makefrag.sv
index 1d25de8..ffbfeca 100644
--- a/isa/rv64ui/Makefrag.sv
+++ b/isa/rv64ui/Makefrag.sv
@@ -11,6 +11,7 @@ rv64ui_sv_tests = \
 	sv_add_elwidth \
 	sv_addw_elwidth \
 	sv_ld_elwidth \
+	sv_st_elwidth \
 	sv_beq \
 
 rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sv_tests))
diff --git a/isa/rv64ui/sv_st_elwidth.S b/isa/rv64ui/sv_st_elwidth.S
new file mode 100644
index 0000000..0900c9b
--- /dev/null
+++ b/isa/rv64ui/sv_st_elwidth.S
@@ -0,0 +1,100 @@
+#include "riscv_test.h"
+#include "sv_test_macros.h"
+
+RVTEST_RV64U        # Define TVM used by program.
+
+#define SV_ELWIDTH_TEST( sinst, vl, elwidth, wid1, wid2, \
+                         testdata, expect1, expect2, expect3 ) \
+                                                        \
+        la x12, testtarget ;                              \
+        la x13, (testtarget+elwidth);                              \
+        la x14, (testtarget+elwidth*2);                              \
+        la x15, (testtarget+elwidth*3);                              \
+        la x16, (testtarget+elwidth*4);                              \
+        la x17, (testtarget+elwidth*5);                              \
+                                                        \
+        li t0, 0xa5a5a5a5a5a5a5a5;                          \
+        la t1, testtarget;                                      \
+        sd t0, 0(t1);                                      \
+        sd t0, elwidth(t1);                                      \
+        sd t0, elwidth*2(t1);                                      \
+                                                        \
+        ld x28, testdata;                                      \
+        ld x29, (testdata+elwidth);                                      \
+        ld x30, (testdata+elwidth*2);                                      \
+                                                        \
+        SET_SV_MVL( vl);                                  \
+        SET_SV_2CSRS( SV_REG_CSR( 1, 12, wid1, 12, 1),        \
+                      SV_REG_CSR( 1, 28, wid2, 28, 1));       \
+        SET_SV_VL( vl );                                   \
+                                                        \
+        sinst   x28, 0(x12);                              \
+                                                        \
+        CLR_SV_CSRS();                                  \
+        SET_SV_VL( 1);                                   \
+        SET_SV_MVL( 1);                                  \
+                                                        \
+        ld x28, testtarget;                                      \
+        ld x29, (testtarget+elwidth);                                      \
+        ld x30, (testtarget+elwidth*2);                                      \
+                                                        \
+        TEST_SV_IMM( x28, expect1 );                         \
+        TEST_SV_IMM( x29, expect2 );                       \
+        TEST_SV_IMM( x30, expect3 );
+
+
+# SV test: vector-vector add
+#
+# sets up x3 and x4 with data, sets VL to 2, and carries out
+# an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
+
+# Test code region.
+RVTEST_CODE_BEGIN   # Start of test code.
+
+        SV_ELWIDTH_TEST(  sd , 2, 8, SV_W_DFLT, SV_W_DFLT, testdata1,
+                0x8979695949392919,  0x8777675747372717,  0xa5a5a5a5a5a5a5a5 )
+        SV_ELWIDTH_TEST(  sd , 3, 8, SV_W_DFLT, SV_W_DFLT, testdata1,
+                0x8979695949392919,  0x8777675747372717,  0x8676665646362616 )
+        SV_ELWIDTH_TEST(  sd , 3, 8, SV_W_16BIT, SV_W_DFLT, testdata1,
+                0xa5a5261627172919,  0xa5a5a5a5a5a5a5a5,  0xa5a5a5a5a5a5a5a5 )
+        SV_ELWIDTH_TEST(  sd , 5, 8, SV_W_16BIT, SV_W_32BIT, testdata1,
+                0x6757271769592919,  0xa5a5a5a5a5a52616,  0xa5a5a5a5a5a5a5a5 )
+        SV_ELWIDTH_TEST(  sd , 5, 8, SV_W_32BIT, SV_W_16BIT, testdata1,
+                0x0000493900002919,  0x0000897900006959,  0xa5a5a5a500002717 )
+        SV_ELWIDTH_TEST(  sd , 7, 8, SV_W_16BIT, SV_W_8BIT, testdata1,
+                0x0049003900290019,  0xa5a5007900690059,  0xa5a5a5a5a5a5a5a5 )
+        SV_ELWIDTH_TEST(  sd , 11, 8, SV_W_8BIT, SV_W_16BIT, testdata1,
+                0x7757371779593919,  0xa5a5a5a5a5563616,  0xa5a5a5a5a5a5a5a5 )
+        RVTEST_PASS           # Signal success.
+fail:
+        RVTEST_FAIL
+RVTEST_CODE_END     # End of test code.
+
+# Input data section.
+# This section is optional, and this data is NOT saved in the output.
+.data
+        .align 3
+testdata1:
+        .dword 0x8979695949392919
+        .dword 0x8777675747372717
+        .dword 0x8676665646362616
+        .dword 0x8272625242322212
+        .dword 0x8171615141312111
+        .dword 0x8373635343332313
+testtarget:
+        .dword 0x0
+        .dword 0x0
+        .dword 0x0
+        .dword 0x0
+        .dword 0x0
+        .dword 0x0
+
+# Output data section.
+RVTEST_DATA_BEGIN   # Start of test output data region.
+        .align 3
+result:
+        .dword -1
+        .dword -1
+        .dword -1
+RVTEST_DATA_END     # End of test output data region.
+