From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 1 Oct 2018 11:02:56 +0000 (+0100)
Subject: update sv test comments
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=6434d21796630d8fc3bf5288ed2eacc1bb303dbd

update sv test comments
---

diff --git a/isa/rv64ui/sv_addi.S b/isa/rv64ui/sv_addi.S
index e86a3f3..123052c 100644
--- a/isa/rv64ui/sv_addi.S
+++ b/isa/rv64ui/sv_addi.S
@@ -4,7 +4,9 @@
 RVTEST_RV64U        # Define TVM used by program.
 
 
-# SV test: sets up x3 and x4 with data, sets VL to 2, and carries out
+# SV test: vector-vector add
+#
+# sets up x3 and x4 with data, sets VL to 2, and carries out
 # an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
 
 # Test code region.
diff --git a/isa/rv64ui/sv_addi_redirect.S b/isa/rv64ui/sv_addi_redirect.S
index 980cb5b..61e9284 100644
--- a/isa/rv64ui/sv_addi_redirect.S
+++ b/isa/rv64ui/sv_addi_redirect.S
@@ -3,7 +3,9 @@
 
 RVTEST_RV64U        # Define TVM used by program.
 
-# SV test: sets up x3 and x4 with data, then sets up SV redirection
+# SV test: vector-vector (redirected) add
+#
+# sets up x3 and x4 with data, then sets up SV redirection
 # from register x16 to register x3 with a VL of 2.  the add is carried out
 # on x16 and the redirection means "actually, we want to do that add on x3"
 # and the VL means "actually we want to do that add on x3 *AND* x4"
diff --git a/isa/rv64ui/sv_addi_scalar_src.S b/isa/rv64ui/sv_addi_scalar_src.S
index 2d1e974..fda4e0c 100644
--- a/isa/rv64ui/sv_addi_scalar_src.S
+++ b/isa/rv64ui/sv_addi_scalar_src.S
@@ -4,7 +4,9 @@
 RVTEST_RV64U        # Define TVM used by program.
 
 
-# SV test: sets up x6 data as a scalar, sets VL to 2, and carries out
+# SV test: scalar-to-vector add
+#
+# sets up x6 data as a scalar, sets VL to 2, and carries out
 # an "add 1 to x6 and store in x3".
 # which actually means:
 # "add add 1 to x6 and store in x3" *AND*