From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 31 Oct 2018 00:22:28 +0000 (+0000)
Subject: test of fp16 elwidth
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=6e0b8f937753fddb607045051bd6c9322f16bc38

test of fp16 elwidth
---

diff --git a/isa/rv64uf/sv_fadd_elwidth.S b/isa/rv64uf/sv_fadd_elwidth.S
index f0620f2..9b5bc0d 100644
--- a/isa/rv64uf/sv_fadd_elwidth.S
+++ b/isa/rv64uf/sv_fadd_elwidth.S
@@ -18,7 +18,7 @@ RVTEST_CODE_BEGIN   # Start of test code.
         SV_FLW_DATA( f7, testdata+12, 0)
 
         SET_SV_MVL(2)
-        SET_SV_3CSRS( SV_REG_CSR(0, 2, 0, 2, 1),
+        SET_SV_3CSRS( SV_REG_CSR(0, 2, 2, 2, 1),
                       SV_REG_CSR(0, 4, 0, 4, 1),
                       SV_REG_CSR(0, 6, 0, 6, 1) )
         SET_SV_VL(2)
@@ -47,10 +47,8 @@ testdata:
         .float 1.0
         .float 2.0
 answer:
-        #.word 0x5140
-        #.word 0x5100
-        .float 42.0
-        .float 44.0
+        .word 0xffff5140
+        .word 0xffff5180
 
 # Output data section.
 RVTEST_DATA_BEGIN   # Start of test output data region.