From: Tim Newsome <tim@sifive.com>
Date: Tue, 3 Jul 2018 20:54:13 +0000 (-0700)
Subject: rwatch/watch on explicit address
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=8519aa3f0ccf4032249b346fbd67855da99b5f3c

rwatch/watch on explicit address

Newer gdb requires more debug info in order to "watch data" in this
test. I'm not sure how to make that debug info happen, so instead we
tell it the address to use.
---

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index 257f8d4..bd9babc 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -692,7 +692,8 @@ class TriggerLoadAddressInstant(TriggerTest):
         self.gdb.c()
         read_loop = self.gdb.p("&read_loop")
         read_again = self.gdb.p("&read_again")
-        self.gdb.command("rwatch data")
+        data = self.gdb.p("&data")
+        self.gdb.command("rwatch *0x%x" % data)
         self.gdb.c()
         # Accept hitting the breakpoint before or after the load instruction.
         assertIn(self.gdb.p("$pc"), [read_loop, read_loop + 4])
@@ -719,7 +720,8 @@ class TriggerStoreAddressInstant(TriggerTest):
         self.gdb.command("b just_before_write_loop")
         self.gdb.c()
         write_loop = self.gdb.p("&write_loop")
-        self.gdb.command("watch data")
+        data = self.gdb.p("&data")
+        self.gdb.command("watch *0x%x" % data)
         self.gdb.c()
         # Accept hitting the breakpoint before or after the store instruction.
         assertIn(self.gdb.p("$pc"), [write_loop, write_loop + 4])