From: Daniel Benusovich Date: Thu, 22 Nov 2018 23:35:30 +0000 (-0800) Subject: Updating SV_ELWIDTH_TEST to accept code... parameter to account for differing assembl... X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=8ab3501053bf57e2392968f731ae5c794f837101 Updating SV_ELWIDTH_TEST to accept code... parameter to account for differing assembly instruction formats --- diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h index 5459c35..b17a5bf 100644 --- a/isa/macros/simplev/sv_test_macros.h +++ b/isa/macros/simplev/sv_test_macros.h @@ -109,8 +109,13 @@ fmv.x.s x2, freg; \ bne x2, x1, fail; -#define SV_ELWIDTH_TEST(code, load_instruction, testdata, elwidth, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \ - expect1, expect2, expect3 ) \ +#define SV_ELWIDTH_NONLOAD_TEST(code, load_instruction, testdata, elwidth, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \ + expect1, expect2, expect3 ) \ + SV_ELDWIDTH_TEST(load_instruction, testdata, elwidth, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \ + expect1, expect2, expect3, code x28, x15, x12) \ + +#define SV_ELWIDTH_TEST(load_instruction, testdata, elwidth, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \ + expect1, expect2, expect3, code... ) \ \ load_instruction( x12, testdata , 0); \ load_instruction( x13, testdata+elwidth , 0); \ @@ -129,7 +134,7 @@ SV_REG_CSR( 1, 28, wid3, 28, isvec3)); \ SET_SV_VL( vl ); \ \ - code x28, x15, x12; \ + code; \ \ CLR_SV_CSRS(); \ SET_SV_VL( 1); \