From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Oct 2018 03:53:18 +0000 (+0100)
Subject: add 3rd register to c.swsp
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=9155b9ad03631adfe2c179c64dd8bb83ef27539e

add 3rd register to c.swsp
---

diff --git a/isa/rv64uc/sv_c_swsp.S b/isa/rv64uc/sv_c_swsp.S
index 11d0229..c29a9b4 100644
--- a/isa/rv64uc/sv_c_swsp.S
+++ b/isa/rv64uc/sv_c_swsp.S
@@ -19,11 +19,12 @@ RVTEST_CODE_BEGIN
 
         li          a2, 1000;
         li          a3, 1001;
+        li          a4, 1004;
 
-        SET_SV_MVL(2)
+        SET_SV_MVL(3)
         SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1, 0),
                       SV_REG_CSR(1, 2, 0, 2, 1, 0) )
-        SET_SV_VL(2)
+        SET_SV_VL(3)
 
   mv a1, sp
   la sp, data;
@@ -42,15 +43,14 @@ RVTEST_CODE_BEGIN
 
   mv sp, a1
 
-  li          a2, 0;
-  li          a3, 0;
-
   la a2, data;
   lw a4, 0(a2);
   lw a5, 4(a2);
+  lw a6, 8(a2);
 
         TEST_SV_IMM(a4, 1000) 
         TEST_SV_IMM(a5, 1001)
+        TEST_SV_IMM(a6, 1004)
 
   .option pop
 
@@ -64,6 +64,7 @@ RVTEST_CODE_END     # End of test code.
 data:
   .word 0;
   .word 0;
+  .word 0;
 
 RVTEST_DATA_BEGIN