From: Tim Newsome <tim@sifive.com>
Date: Wed, 22 Aug 2018 20:47:26 +0000 (-0700)
Subject: Merge branch 'master' of https://github.com/riscv/riscv-tests
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=995207c1196d970173e1513535e8341542111102;hp=51ec34e28541f8c89cd89a6a9c137bd32ba71c29

Merge branch 'master' of https://github.com/riscv/riscv-tests
---

diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S
index 0579806..82f202a 100644
--- a/isa/rv64si/scall.S
+++ b/isa/rv64si/scall.S
@@ -34,8 +34,8 @@ RVTEST_CODE_BEGIN
   # Otherwise, if in S mode, then U mode must exist and we don't need to check.
   li t0, MSTATUS_MPP
   csrc mstatus, t0
-  csrr t1, mstatus
-  and t0, t0, t1
+  csrr t2, mstatus
+  and t0, t0, t2
   beqz t0, 1f
 
   # If U mode doesn't exist, mcause should indicate ECALL from M mode.