From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 30 Oct 2018 07:53:43 +0000 (+0000)
Subject: add fp add elwidth single-precision test
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=c7758747574b99c11d9083b7235887569de61d19

add fp add elwidth single-precision test
---

diff --git a/isa/Makefile b/isa/Makefile
index b096935..8cdd3d5 100644
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -14,6 +14,7 @@ include $(src_dir)/rv64uc/Makefrag.sv
 include $(src_dir)/rv64um/Makefrag
 include $(src_dir)/rv64ua/Makefrag
 include $(src_dir)/rv64uf/Makefrag
+include $(src_dir)/rv64uf/Makefrag.sv
 include $(src_dir)/rv64ud/Makefrag
 include $(src_dir)/rv64ud/Makefrag.sv
 include $(src_dir)/rv64si/Makefrag
diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index 0395755..6c671df 100644
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -41,6 +41,10 @@
         la      x1, from; \
         fld     reg, offs(x1)
 
+#define SV_FLW_DATA( reg, from, offs ) \
+        la      x1, from; \
+        flw     reg, offs(x1)
+
 #define TEST_SV_IMM( reg, imm ) \
         li      t6, ((imm) & 0xffffffffffffffff); \
         bne     reg, t6, fail
@@ -54,6 +58,15 @@
         fmv.x.d x2, freg; \
         bne     x2, x1, fail
 
+#define TEST_SV_FW( flags, freg, from, offs ) \
+        fsflags x2, x0; \
+        li      x1, flags; \
+        bne     x2, x1, fail; \
+        la      x1, from; \
+        lw      x1, offs(x1); \
+        fmv.x.s x2, freg; \
+        bne     x2, x1, fail
+
 #define SV_W_DFLT 0
 #define SV_W_8BIT 1
 #define SV_W_16BIT 2
diff --git a/isa/rv64uf/Makefrag.sv b/isa/rv64uf/Makefrag.sv
new file mode 100644
index 0000000..ed9c764
--- /dev/null
+++ b/isa/rv64uf/Makefrag.sv
@@ -0,0 +1,12 @@
+#=======================================================================
+# Makefrag for rv64uf sv tests
+#-----------------------------------------------------------------------
+
+rv64uf_sv_tests = \
+	sv_fadd_elwidth \
+
+rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sv_tests))
+rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sv_tests))
+
+spike_tests += $(rv64uf_p_tests) $(rv64uf_v_tests)
+
diff --git a/isa/rv64uf/sv_fadd_elwidth.S b/isa/rv64uf/sv_fadd_elwidth.S
new file mode 100644
index 0000000..f0620f2
--- /dev/null
+++ b/isa/rv64uf/sv_fadd_elwidth.S
@@ -0,0 +1,63 @@
+#include "riscv_test.h"
+#include "sv_test_macros.h"
+
+RVTEST_RV64UF
+
+
+# SV test: vector-vector fadd
+#
+# sets up x3 and x4 with data, sets VL to 2, and carries out
+# an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
+
+# Test code region.
+RVTEST_CODE_BEGIN   # Start of test code.
+
+        SV_FLW_DATA( f4, testdata+0 , 0)
+        SV_FLW_DATA( f5, testdata+4, 0)
+        SV_FLW_DATA( f6, testdata+8, 0)
+        SV_FLW_DATA( f7, testdata+12, 0)
+
+        SET_SV_MVL(2)
+        SET_SV_3CSRS( SV_REG_CSR(0, 2, 0, 2, 1),
+                      SV_REG_CSR(0, 4, 0, 4, 1),
+                      SV_REG_CSR(0, 6, 0, 6, 1) )
+        SET_SV_VL(2)
+
+        fadd.s f2, f4, f6;
+
+        CLR_SV_CSRS()
+        SET_SV_VL(1)
+        SET_SV_MVL(1)
+
+        TEST_SV_FW(0, f2, answer+0, 0) 
+        TEST_SV_FW(0, f3, answer+4, 0) 
+
+        RVTEST_PASS           # Signal success.
+fail:
+        RVTEST_FAIL
+RVTEST_CODE_END     # End of test code.
+
+# Input data section.
+# This section is optional, and this data is NOT saved in the output.
+.data
+        .align 3
+testdata:
+        .float 41.0
+        .float 42.0
+        .float 1.0
+        .float 2.0
+answer:
+        #.word 0x5140
+        #.word 0x5100
+        .float 42.0
+        .float 44.0
+
+# Output data section.
+RVTEST_DATA_BEGIN   # Start of test output data region.
+        .align 3
+result:
+        .dword -1
+        .dword -1
+        .dword -1
+RVTEST_DATA_END     # End of test output data region.
+