From: Megan Wachs <megan@sifive.com>
Date: Thu, 18 May 2017 19:09:40 +0000 (-0700)
Subject: debug: Correct the calling for a 32-bit simulation target
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=d74b266e4fa780ec0b42663b752deaa58fda91ae

debug: Correct the calling for a 32-bit simulation target
---

diff --git a/debug/targets.py b/debug/targets.py
index 423ff69..b8557ce 100644
--- a/debug/targets.py
+++ b/debug/targets.py
@@ -107,7 +107,7 @@ class FreedomE300SimTarget(Target):
     openocd_config = "targets/%s/openocd.cfg" % name
 
     def target(self):
-        return testlib.VcsSim(simv=self.sim_cmd, debug=False)
+        return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
 
 class FreedomU500Target(Target):
     name = "freedom-u500"