From: Daniel Benusovich <flyingmonkeys1996@gmail.com>
Date: Fri, 23 Nov 2018 05:38:15 +0000 (-0800)
Subject: Added offset parameter to SV_ELWIDTH_TEST
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=dff417cd34af4a4045552dd3cf45fe1f474fe8d2

Added offset parameter to SV_ELWIDTH_TEST
---

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index dcde682..35a415c 100644
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -109,7 +109,8 @@
         fmv.x.s x2, freg; \
         bne     x2, x1, fail;
 
-#define SV_LOAD_FORMAT_NO_OFFSET(load_instruction, testdata, elwidth)	\
+// Loads the source registers using load_instruction from testdata with a spacing of elwidth
+#define SV_LOAD_FORMAT(load_instruction, testdata, elwidth)	\
         load_instruction( x12, testdata);                             	\
         load_instruction( x13, testdata+elwidth);                       \
         load_instruction( x14, testdata+elwidth*2);                     \
@@ -117,30 +118,42 @@
         load_instruction( x16, testdata+elwidth*4);                     \
         load_instruction( x17, testdata++elwidth*5);  			\
 
-#define SV_LOAD_FORMAT_OFFSET(load_instruction, testdata, elwidth)	\
-        load_instruction( x12, testdata, 0);                            \
-        load_instruction( x13, testdata+elwidth, 0);                    \
-        load_instruction( x14, testdata+elwidth*2, 0);                  \
-        load_instruction( x15, testdata+elwidth*3, 0);                  \
-        load_instruction( x16, testdata+elwidth*4, 0);                  \
-        load_instruction( x17, testdata+elwidth*5, 0);  		\
-
-#define SV_ELWIDTH_TEST(code, load_instruction, testdata, elwidth,				\
- 				vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, 			\
-                 		expect1, expect2, expect3 )					\
-												\
-	SV_ELWIDTH_TEST_INNER(SV_LOAD_FORMAT_OFFSET(load_instruction, testdata, elwidth), 	\
-			vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, 				\
-                 	expect1, expect2, expect3, code x28, x15, x12) 				\
-
+// Loads the source registers using load_instruction from testdata with a spacing of elwidth and offset
+#define SV_LOAD_FORMAT_OFFSET(load_instruction, testdata, elwidth, offset)   \
+        load_instruction( x12, testdata, offset);                            \
+        load_instruction( x13, testdata+elwidth, offset);                    \
+        load_instruction( x14, testdata+elwidth*2, offset);                  \
+        load_instruction( x15, testdata+elwidth*3, offset);                  \
+        load_instruction( x16, testdata+elwidth*4, offset);                  \
+        load_instruction( x17, testdata+elwidth*5, offset);  		     \
+
+// This should be used in all cases where three parameters are formed with an instruction
+// IE addw x28, x15, x12 will be generated
+#define SV_ELWIDTH_TEST(code, load_instruction, testdata, elwidth, offset,				\
+ 				vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, 				\
+                 		expect1, expect2, expect3 )						\
+													\
+	SV_ELWIDTH_TEST_INNER(SV_LOAD_FORMAT_OFFSET(load_instruction, testdata, elwidth, offset), 	\
+			vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, 					\
+                 	expect1, expect2, expect3, code x28, x15, x12) 					\
+
+// This should be used in all cases where two parameters are formed with an instruction
+// IE ld x28 (0)x12 will be generated
 #define SV_ELWIDTH_TEST_LOAD(code, load_instruction, testdata, elwidth,				\
  				vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, 			\
                  		expect1, expect2, expect3 )					\
 												\
-	SV_ELWIDTH_TEST_INNER(SV_LOAD_FORMAT_NO_OFFSET(load_instruction, testdata, elwidth), 	\
+	SV_ELWIDTH_TEST_INNER(SV_LOAD_FORMAT(load_instruction, testdata, elwidth), 		\
 			vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, 				\
                  	expect1, expect2, expect3, code x28, x15, x12) 				\
 
+// This should not be accessed directly. It is meant to be called through higher level macros.
+// If used:
+// 1. The 'load_type' parameter should be a SV_LOAD_FORMAT_* macro to 
+// generate loading instructions.
+// 2. The 'code' parameter should take on the form of the instruction being tested
+// IE addw x28, x15, x12. 
+// Note: The destination register is always 28. The source registers are always 12 and 15
 #define SV_ELWIDTH_TEST_INNER(load_type, vl, wid1, wid2, wid3,		\
  			isvec1, isvec2, isvec3, 			\
                  	expect1, expect2, expect3, code... )            \