From 30dcd148bd02a5f38fe7c59ba65d2957c212b64b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 4 Nov 2018 16:18:31 +0000 Subject: [PATCH] add shape remap fadd unit test --- isa/macros/simplev/sv_test_macros.h | 24 ++++++++ isa/rv64ud/Makefrag.sv | 1 + isa/rv64ud/sv_fadd_remap.S | 88 +++++++++++++++++++++++++++++ 3 files changed, 113 insertions(+) create mode 100644 isa/rv64ud/sv_fadd_remap.S diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h index 6c671df..be324f3 100644 --- a/isa/macros/simplev/sv_test_macros.h +++ b/isa/macros/simplev/sv_test_macros.h @@ -1,8 +1,32 @@ +#define SV_REMAP_CSR(reg0, shape0, reg1, shape1, reg2, shape2) \ + (reg0 | (reg1<<8) | (reg2<<8) | \ + (shape0<<24) | (shape0<<26) | (shape0<<28)) + +#define SV_SHAPE_PERM_XYZ 0 +#define SV_SHAPE_PERM_XZY 1 +#define SV_SHAPE_PERM_YXZ 2 +#define SV_SHAPE_PERM_YZX 3 +#define SV_SHAPE_PERM_ZXY 4 +#define SV_SHAPE_PERM_ZYX 5 + +#define SV_SHAPE_CSR(xd, yd, zd, offs, perm) \ + ((xd-1) | ((yd-1)<<8) | ((zd-1)<<16) | (perm<<24) | \ + ((offs&0x1)<<7) | ((offs&0x2)<<14) | ((offs&0x4)<<21) ) + + #define SV_REG_CSR(type, regkey, elwidth, regidx, isvec) \ (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<15)) #define SV_PRED_CSR(type, regkey, zero, inv, regidx, packed) \ (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (packed<<15)) +#define SET_SV_REMAP_CSR(reg0, shape0, reg1, shape1, reg2, shape2) \ + li x1, SV_REMAP_CSR( reg0, shape0, reg1, shape1, reg2, shape2); \ + csrrw x0, 0x4f7, x1 + +#define SET_SV_SHAPE0_CSR(xd, yd, zd, offs, permute) \ + li x1, SV_SHAPE_CSR( xd, yd, zd, offs, permute); \ + csrrw x0, 0x4f8, x1 + #define SET_SV_CSR( type, regkey, elwidth, regidx, isvec) \ li x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \ csrrw x0, 0x4c0, x1 diff --git a/isa/rv64ud/Makefrag.sv b/isa/rv64ud/Makefrag.sv index 6407239..82590b1 100644 --- a/isa/rv64ud/Makefrag.sv +++ b/isa/rv64ud/Makefrag.sv @@ -4,6 +4,7 @@ rv64ud_sv_tests = \ sv_fadd \ + sv_fadd_remap \ rv64ud_p_tests = $(addprefix rv64ud-p-, $(rv64ud_sv_tests)) rv64ud_v_tests = $(addprefix rv64ud-v-, $(rv64ud_sv_tests)) diff --git a/isa/rv64ud/sv_fadd_remap.S b/isa/rv64ud/sv_fadd_remap.S new file mode 100644 index 0000000..c0af566 --- /dev/null +++ b/isa/rv64ud/sv_fadd_remap.S @@ -0,0 +1,88 @@ +#include "riscv_test.h" +#include "sv_test_macros.h" + +RVTEST_RV64UF + + +# SV test: vector-vector fadd +# +# sets up x3 and x4 with data, sets VL to 2, and carries out +# an "add 1 to x3". which actually means "add 1 to x3 *AND* add 1 to x4" + +# Test code region. +RVTEST_CODE_BEGIN # Start of test code. + + SV_FLD_DATA( f1, testdata , 0) + SV_FLD_DATA( f2, testdata+(1*8) , 0) + SV_FLD_DATA( f3, testdata+(2*8), 0) + SV_FLD_DATA( f4, testdata+(3*8), 0) + SV_FLD_DATA( f5, testdata+(4*8), 0) + SV_FLD_DATA( f6, testdata+(5*8), 0) + SV_FLD_DATA( f7, testdata+(6*8), 0) + SV_FLD_DATA( f8, testdata+(7*8), 0) + SV_FLD_DATA( f9, testdata+(8*8), 0) + SV_FLD_DATA( f10, testdata+(9*8), 0) + SV_FLD_DATA( f11, testdata+(10*8), 0) + SV_FLD_DATA( f12, testdata+(11*8), 0) + + SET_SV_MVL(6) + SET_SV_2CSRS( SV_REG_CSR(0, 1, 0, 1, 1), + SV_REG_CSR(0, 7, 0, 7, 1) ) + SET_SV_REMAP_CSR(7, 0, 0, 0, 0, 0); + SET_SV_SHAPE0_CSR(3, 2, 1, 0, SV_SHAPE_PERM_YXZ ); + SET_SV_VL(6) + + fadd.d f1, f1, f7; + + CLR_SV_CSRS() + SET_SV_VL(1) + SET_SV_MVL(1) + + TEST_SV_FD(0, f1, results, 0) + TEST_SV_FD(0, f2, results+1*8, 0) + TEST_SV_FD(0, f3, results+2*8, 0) + TEST_SV_FD(0, f4, results+3*8, 0) + TEST_SV_FD(0, f5, results+4*8, 0) + TEST_SV_FD(0, f6, results+5*8, 0) + + RVTEST_PASS # Signal success. +fail: + RVTEST_FAIL +RVTEST_CODE_END # End of test code. + +# Input data section. +# This section is optional, and this data is NOT saved in the output. +.data + .align 3 +testdata: + .double 0.0 + .double 1.0 + .double 2.0 + .double 3.0 + .double 4.0 + .double 5.0 + .double 100.0 + .double 200.0 + .double 300.0 + .double 400.0 + .double 500.0 + .double 600.0 + + .align 3 +results: + .double 100.0 + .double 401.0 + .double 202.0 + .double 503.0 + .double 304.0 + .double 605.0 + +# Output data section. +RVTEST_DATA_BEGIN # Start of test output data region. + .align 3 +result: + .dword -1 + .dword -1 + .dword -1 +RVTEST_DATA_END # End of test output data region. + -- 2.30.2