From 542fbb5256afc7c229f7956787e74fdf20590b92 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 10 Nov 2018 11:59:36 +0000 Subject: [PATCH] add sv mulhu elwidth test --- isa/Makefile | 1 + isa/rv64um/Makefrag.sv | 11 ++++ isa/rv64um/sv_mulhu_elwidth.S | 96 +++++++++++++++++++++++++++++++++++ 3 files changed, 108 insertions(+) create mode 100644 isa/rv64um/Makefrag.sv create mode 100644 isa/rv64um/sv_mulhu_elwidth.S diff --git a/isa/Makefile b/isa/Makefile index 5c34d4e..ae093ed 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -12,6 +12,7 @@ include $(src_dir)/rv64ui/Makefrag.sv include $(src_dir)/rv64uc/Makefrag include $(src_dir)/rv64uc/Makefrag.sv include $(src_dir)/rv64um/Makefrag +include $(src_dir)/rv64um/Makefrag.sv include $(src_dir)/rv64ua/Makefrag include $(src_dir)/rv64uf/Makefrag include $(src_dir)/rv64uf/Makefrag.sv diff --git a/isa/rv64um/Makefrag.sv b/isa/rv64um/Makefrag.sv new file mode 100644 index 0000000..308127f --- /dev/null +++ b/isa/rv64um/Makefrag.sv @@ -0,0 +1,11 @@ +#======================================================================= +# Makefrag for rv64um tests +#----------------------------------------------------------------------- + +rv64um_sv_tests = \ + sv_mulhu_elwidth \ + +rv64um_p_tests = $(addprefix rv64um-p-, $(rv64um_sv_tests)) +rv64um_v_tests = $(addprefix rv64um-v-, $(rv64um_sv_tests)) + +spike_tests += $(rv64um_p_tests) $(rv64um_v_tests) diff --git a/isa/rv64um/sv_mulhu_elwidth.S b/isa/rv64um/sv_mulhu_elwidth.S new file mode 100644 index 0000000..0fc599a --- /dev/null +++ b/isa/rv64um/sv_mulhu_elwidth.S @@ -0,0 +1,96 @@ +#include "riscv_test.h" +#include "sv_test_macros.h" + +RVTEST_RV64U # Define TVM used by program. + +// TODO: add extra "code" argument and "testdata" argument, +// replace "sraw" with "code" +// TODO: move SV_ELWIDTH_TEST to sv_test_macros.h +// TODO: probably remove testing of x15 and x16 (or pass in as extra args?) + +#define SV_ELWIDTH_TEST( vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \ + expect1, expect2, expect3 ) \ + \ + SV_LDD_DATA( x12, testdata , 0); \ + SV_LDD_DATA( x13, testdata+8 , 0); \ + SV_LDD_DATA( x14, testdata+16, 0); \ + SV_LDD_DATA( x15, testdata+24, 0); \ + SV_LDD_DATA( x16, testdata+32, 0); \ + SV_LDD_DATA( x17, testdata+40, 0); \ + \ + li x28, 0xa5a5a5a5a5a5a5a5; \ + li x29, 0xa5a5a5a5a5a5a5a5; \ + li x30, 0xa5a5a5a5a5a5a5a5; \ + \ + SET_SV_MVL( vl ); \ + SET_SV_2CSRS( SV_REG_CSR( 1, 15, wid1, 15, isvec1), \ + SV_REG_CSR( 1, 12, wid2, 12, isvec2) ); \ + SET_SV_CSR2( 1, 28, wid3, 28, isvec3); \ + SET_SV_VL( vl ); \ + \ + mulhu x28, x15, x12; \ + \ + CLR_SV_CSRS(); \ + SET_SV_VL( 1); \ + SET_SV_MVL( 1); \ + \ + TEST_SV_IMMW( x28, expect1 ); \ + TEST_SV_IMMW( x29, expect2 ); \ + TEST_SV_IMMW( x30, expect3 ); + + +# SV test: vector-vector add +# +# sets up x3 and x4 with data, sets VL to 2, and carries out +# an "add 1 to x3". which actually means "add 1 to x3 *AND* add 1 to x4" + +# Test code region. +RVTEST_CODE_BEGIN # Start of test code. + + # TODO: add "sraw" argument, add testdata argument + SV_ELWIDTH_TEST( 3, 0, 0, 0, 1, 1, 1, + 0xffffffff7fff8000, 0x000000000001fefe, 0xfffffffffe000000 ) +/* + SV_ELWIDTH_TEST( 3, 0, 0, 3, 1, 1, 1, + 0x7fffc000, 0x0001fefe, 0xfe010000 ) + SV_ELWIDTH_TEST( 3, 2, 2, 0, 1, 1, 1, + 0x00000000, 0x00007fff, 0x0000a9a8 ) + SV_ELWIDTH_TEST( 3, 2, 2, 2, 1, 1, 1, + 0x7fff0000, 0xa5a5a9a8, 0xa5a5a5a5 ) + SV_ELWIDTH_TEST( 3, 2, 2, 1, 1, 1, 1, + 0xa5a8ff00, 0xa5a5a5a5, 0xa5a5a5a5 ) + SV_ELWIDTH_TEST( 3, 3, 3, 1, 1, 1, 1, + 0xa500fe00, 0xa5a5a5a5, 0xa5a5a5a5 ) + SV_ELWIDTH_TEST( 3, 2, 3, 3, 1, 1, 1, + 0x00004000, 0x0000aaaa, 0x0000fd7e ) + SV_ELWIDTH_TEST( 3, 1, 1, 2, 1, 1, 1, + 0xa5a5001900110009, 0xa5a5a5a5a5a5a5a5, 0xa5a5a5a5a5a5a5a5 ) + SV_ELWIDTH_TEST( 3, 1, 1, 1, 1, 1, 1, + 0xa5a5a5a5a5191109, 0xa5a5a5a5a5a5a5a5, 0xa5a5a5a5a5a5a5a5 ) +*/ + RVTEST_PASS # Signal success. +fail: + RVTEST_FAIL +RVTEST_CODE_END # End of test code. + +# Input data section. +# This section is optional, and this data is NOT saved in the output. +.data + .align 3 +testdata: + .dword 0xffffffff80000000 + .dword 0xaaaaaaaaaaaaaaab + .dword 0xffffffffff000000 + .dword 0xffffffffffff8000 + .dword 0x000000000002fe7d + .dword 0xffffffffff000000 + +# Output data section. +RVTEST_DATA_BEGIN # Start of test output data region. + .align 3 +result: + .dword -1 + .dword -1 + .dword -1 +RVTEST_DATA_END # End of test output data region. + -- 2.30.2