From 7155726ad6612a7f87318d84ac496672f9bbc8ce Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 20 Sep 2015 23:38:00 -0700 Subject: [PATCH] Remove Hwacha v3 tests --- benchmarks/Makefile | 6 +- benchmarks/mm/bmark.mk | 1 - benchmarks/mm/common.h | 1 - benchmarks/mm/hwacha.S | 94 - benchmarks/mm/hwacha.h | 140 - benchmarks/mm/mm_main.c | 37 +- benchmarks/vec-cmplxmult/bmark.mk | 30 - benchmarks/vec-cmplxmult/cmplxmult_gendata.pl | 117 - benchmarks/vec-cmplxmult/dataset.h | 1553 -- benchmarks/vec-cmplxmult/dataset_test.h | 29 - benchmarks/vec-cmplxmult/vec_cmplxmult_asm.S | 148 - benchmarks/vec-cmplxmult/vec_cmplxmult_main.c | 319 - benchmarks/vec-fft/bmark.mk | 41 - benchmarks/vec-fft/cvt16.c | 122 - benchmarks/vec-fft/cvt16.h | 19 - benchmarks/vec-fft/cvt_fft.c | 39 - benchmarks/vec-fft/data.c | 23 - benchmarks/vec-fft/dc_data.c | 14 - benchmarks/vec-fft/fft-data-gen | 84 - benchmarks/vec-fft/fft_const.h | 71 - benchmarks/vec-fft/fft_cos_data.c | 8 - benchmarks/vec-fft/fft_dc_float.c | 8 - benchmarks/vec-fft/fft_gaussian_float.c | 8 - benchmarks/vec-fft/vec-fft.c | 171 - benchmarks/vec-fft/vec-fft.h | 21 - benchmarks/vec-fft/vec-fft_gaussian.c | 14 - benchmarks/vec-fft/vec-fft_main.c | 302 - benchmarks/vec-fft/vec-vfft.S | 245 - benchmarks/vec-matmul/bmark.mk | 30 - benchmarks/vec-matmul/dataset.h | 635 - benchmarks/vec-matmul/dataset_test.h | 41 - benchmarks/vec-matmul/matmul_gendata.pl | 200 - benchmarks/vec-matmul/vec_matmul_asm.S | 345 - benchmarks/vec-matmul/vec_matmul_main.c | 207 - benchmarks/vec-vvadd/bmark.mk | 30 - benchmarks/vec-vvadd/dataset.h | 173 - benchmarks/vec-vvadd/dataset_test.h | 20 - benchmarks/vec-vvadd/vec_vvadd_asm.S | 110 - benchmarks/vec-vvadd/vec_vvadd_main.c | 200 - benchmarks/vec-vvadd/vvadd_gendata.pl | 139 - env | 2 +- isa/Makefile | 20 +- isa/macros/scalar/test_macros.h | 123 - isa/rv64sv/Makefrag | 14 - isa/rv64sv/illegal_cfg_nfpr.S | 93 - isa/rv64sv/illegal_cfg_nxpr.S | 92 - isa/rv64sv/illegal_inst.S | 99 - isa/rv64sv/illegal_tvec_regid.S | 51 - isa/rv64sv/illegal_vt_inst.S | 107 - isa/rv64sv/illegal_vt_regid.S | 53 - isa/rv64sv/ma_utld.S | 103 - isa/rv64sv/ma_utsd.S | 105 - isa/rv64sv/ma_vld.S | 104 - isa/rv64sv/ma_vsd.S | 107 - isa/rv64sv/ma_vt_inst.S | 99 - isa/rv64sv/privileged_inst.S | 100 - isa/rv64uf/Makefrag | 8 +- isa/rv64ui/Makefrag | 18 +- isa/rv64uv/Makefrag | 34 - isa/rv64uv/amoadd_d.S | 58 - isa/rv64uv/amoadd_w.S | 58 - isa/rv64uv/amoand_d.S | 58 - isa/rv64uv/amoand_w.S | 58 - isa/rv64uv/amomax_d.S | 61 - isa/rv64uv/amomax_w.S | 61 - isa/rv64uv/amomaxu_d.S | 61 - isa/rv64uv/amomaxu_w.S | 61 - isa/rv64uv/amomin_d.S | 65 - isa/rv64uv/amomin_w.S | 62 - isa/rv64uv/amominu_d.S | 61 - isa/rv64uv/amominu_w.S | 61 - isa/rv64uv/amoor_d.S | 58 - isa/rv64uv/amoor_w.S | 58 - isa/rv64uv/amoswap_d.S | 58 - isa/rv64uv/amoswap_w.S | 58 - isa/rv64uv/amoxor_d.S | 60 - isa/rv64uv/amoxor_w.S | 60 - isa/rv64uv/beq.S | 96 - isa/rv64uv/bge.S | 99 - isa/rv64uv/bgeu.S | 99 - isa/rv64uv/blt.S | 96 - isa/rv64uv/bltu.S | 96 - isa/rv64uv/bne.S | 96 - isa/rv64uv/data_d.h | 4098 ---- isa/rv64uv/data_fd.h | 4098 ---- isa/rv64uv/data_fw.h | 4099 ---- isa/rv64uv/data_w.h | 16387 ---------------- isa/rv64uv/fcvt.S | 75 - isa/rv64uv/fence.S | 61 - isa/rv64uv/fld.S | 62 - isa/rv64uv/flw.S | 62 - isa/rv64uv/fma.S | 81 - isa/rv64uv/fma_many.S | 182 - isa/rv64uv/fmovn.S | 63 - isa/rv64uv/fmovz.S | 64 - isa/rv64uv/fsd.S | 62 - isa/rv64uv/fsw.S | 62 - isa/rv64uv/imul.S | 85 - isa/rv64uv/keepcfg.S | 85 - isa/rv64uv/lb.S | 64 - isa/rv64uv/lbu.S | 64 - isa/rv64uv/ld.S | 62 - isa/rv64uv/lh.S | 64 - isa/rv64uv/lhu.S | 64 - isa/rv64uv/lw.S | 64 - isa/rv64uv/lwu.S | 64 - isa/rv64uv/movn.S | 61 - isa/rv64uv/movz.S | 62 - isa/rv64uv/sb.S | 74 - isa/rv64uv/sd.S | 62 - isa/rv64uv/sh.S | 74 - isa/rv64uv/sw.S | 74 - isa/rv64uv/utidx.S | 53 - isa/rv64uv/vfmsv_d.S | 57 - isa/rv64uv/vfmsv_s.S | 57 - isa/rv64uv/vfmvv.S | 55 - isa/rv64uv/vmsv.S | 56 - isa/rv64uv/vmvv.S | 54 - isa/rv64uv/vsetcfg.S | 561 - isa/rv64uv/vsetcfgi.S | 561 - isa/rv64uv/vsetvl.S | 561 - isa/rv64uv/vvadd_branch.S | 144 - isa/rv64uv/vvadd_d.S | 133 - isa/rv64uv/vvadd_fd.S | 79 - isa/rv64uv/vvadd_fw.S | 79 - isa/rv64uv/vvadd_packed.S | 107 - isa/rv64uv/vvadd_w.S | 88 - isa/rv64uv/vvmul_d.S | 76 - isa/rv64uv/wakeup.S | 160 - mt/Makefile | 2 +- 130 files changed, 17 insertions(+), 42131 deletions(-) delete mode 100644 benchmarks/mm/hwacha.S delete mode 100644 benchmarks/mm/hwacha.h delete mode 100644 benchmarks/vec-cmplxmult/bmark.mk delete mode 100755 benchmarks/vec-cmplxmult/cmplxmult_gendata.pl delete mode 100644 benchmarks/vec-cmplxmult/dataset.h delete mode 100644 benchmarks/vec-cmplxmult/dataset_test.h delete mode 100644 benchmarks/vec-cmplxmult/vec_cmplxmult_asm.S delete mode 100644 benchmarks/vec-cmplxmult/vec_cmplxmult_main.c delete mode 100644 benchmarks/vec-fft/bmark.mk delete mode 100644 benchmarks/vec-fft/cvt16.c delete mode 100644 benchmarks/vec-fft/cvt16.h delete mode 100644 benchmarks/vec-fft/cvt_fft.c delete mode 100644 benchmarks/vec-fft/data.c delete mode 100644 benchmarks/vec-fft/dc_data.c delete mode 100755 benchmarks/vec-fft/fft-data-gen delete mode 100644 benchmarks/vec-fft/fft_const.h delete mode 100644 benchmarks/vec-fft/fft_cos_data.c delete mode 100644 benchmarks/vec-fft/fft_dc_float.c delete mode 100644 benchmarks/vec-fft/fft_gaussian_float.c delete mode 100644 benchmarks/vec-fft/vec-fft.c delete mode 100644 benchmarks/vec-fft/vec-fft.h delete mode 100644 benchmarks/vec-fft/vec-fft_gaussian.c delete mode 100644 benchmarks/vec-fft/vec-fft_main.c delete mode 100644 benchmarks/vec-fft/vec-vfft.S delete mode 100644 benchmarks/vec-matmul/bmark.mk delete mode 100644 benchmarks/vec-matmul/dataset.h delete mode 100644 benchmarks/vec-matmul/dataset_test.h delete mode 100755 benchmarks/vec-matmul/matmul_gendata.pl delete mode 100644 benchmarks/vec-matmul/vec_matmul_asm.S delete mode 100644 benchmarks/vec-matmul/vec_matmul_main.c delete mode 100644 benchmarks/vec-vvadd/bmark.mk delete mode 100644 benchmarks/vec-vvadd/dataset.h delete mode 100644 benchmarks/vec-vvadd/dataset_test.h delete mode 100644 benchmarks/vec-vvadd/vec_vvadd_asm.S delete mode 100644 benchmarks/vec-vvadd/vec_vvadd_main.c delete mode 100755 benchmarks/vec-vvadd/vvadd_gendata.pl delete mode 100644 isa/rv64sv/Makefrag delete mode 100644 isa/rv64sv/illegal_cfg_nfpr.S delete mode 100644 isa/rv64sv/illegal_cfg_nxpr.S delete mode 100644 isa/rv64sv/illegal_inst.S delete mode 100644 isa/rv64sv/illegal_tvec_regid.S delete mode 100644 isa/rv64sv/illegal_vt_inst.S delete mode 100644 isa/rv64sv/illegal_vt_regid.S delete mode 100644 isa/rv64sv/ma_utld.S delete mode 100644 isa/rv64sv/ma_utsd.S delete mode 100644 isa/rv64sv/ma_vld.S delete mode 100644 isa/rv64sv/ma_vsd.S delete mode 100644 isa/rv64sv/ma_vt_inst.S delete mode 100644 isa/rv64sv/privileged_inst.S delete mode 100644 isa/rv64uv/Makefrag delete mode 100644 isa/rv64uv/amoadd_d.S delete mode 100644 isa/rv64uv/amoadd_w.S delete mode 100644 isa/rv64uv/amoand_d.S delete mode 100644 isa/rv64uv/amoand_w.S delete mode 100644 isa/rv64uv/amomax_d.S delete mode 100644 isa/rv64uv/amomax_w.S delete mode 100644 isa/rv64uv/amomaxu_d.S delete mode 100644 isa/rv64uv/amomaxu_w.S delete mode 100644 isa/rv64uv/amomin_d.S delete mode 100644 isa/rv64uv/amomin_w.S delete mode 100644 isa/rv64uv/amominu_d.S delete mode 100644 isa/rv64uv/amominu_w.S delete mode 100644 isa/rv64uv/amoor_d.S delete mode 100644 isa/rv64uv/amoor_w.S delete mode 100644 isa/rv64uv/amoswap_d.S delete mode 100644 isa/rv64uv/amoswap_w.S delete mode 100644 isa/rv64uv/amoxor_d.S delete mode 100644 isa/rv64uv/amoxor_w.S delete mode 100644 isa/rv64uv/beq.S delete mode 100644 isa/rv64uv/bge.S delete mode 100644 isa/rv64uv/bgeu.S delete mode 100644 isa/rv64uv/blt.S delete mode 100644 isa/rv64uv/bltu.S delete mode 100644 isa/rv64uv/bne.S delete mode 100644 isa/rv64uv/data_d.h delete mode 100644 isa/rv64uv/data_fd.h delete mode 100644 isa/rv64uv/data_fw.h delete mode 100644 isa/rv64uv/data_w.h delete mode 100644 isa/rv64uv/fcvt.S delete mode 100644 isa/rv64uv/fence.S delete mode 100644 isa/rv64uv/fld.S delete mode 100644 isa/rv64uv/flw.S delete mode 100644 isa/rv64uv/fma.S delete mode 100644 isa/rv64uv/fma_many.S delete mode 100644 isa/rv64uv/fmovn.S delete mode 100644 isa/rv64uv/fmovz.S delete mode 100644 isa/rv64uv/fsd.S delete mode 100644 isa/rv64uv/fsw.S delete mode 100644 isa/rv64uv/imul.S delete mode 100644 isa/rv64uv/keepcfg.S delete mode 100644 isa/rv64uv/lb.S delete mode 100644 isa/rv64uv/lbu.S delete mode 100644 isa/rv64uv/ld.S delete mode 100644 isa/rv64uv/lh.S delete mode 100644 isa/rv64uv/lhu.S delete mode 100644 isa/rv64uv/lw.S delete mode 100644 isa/rv64uv/lwu.S delete mode 100644 isa/rv64uv/movn.S delete mode 100644 isa/rv64uv/movz.S delete mode 100644 isa/rv64uv/sb.S delete mode 100644 isa/rv64uv/sd.S delete mode 100644 isa/rv64uv/sh.S delete mode 100644 isa/rv64uv/sw.S delete mode 100644 isa/rv64uv/utidx.S delete mode 100644 isa/rv64uv/vfmsv_d.S delete mode 100644 isa/rv64uv/vfmsv_s.S delete mode 100644 isa/rv64uv/vfmvv.S delete mode 100644 isa/rv64uv/vmsv.S delete mode 100644 isa/rv64uv/vmvv.S delete mode 100644 isa/rv64uv/vsetcfg.S delete mode 100644 isa/rv64uv/vsetcfgi.S delete mode 100644 isa/rv64uv/vsetvl.S delete mode 100644 isa/rv64uv/vvadd_branch.S delete mode 100644 isa/rv64uv/vvadd_d.S delete mode 100644 isa/rv64uv/vvadd_fd.S delete mode 100644 isa/rv64uv/vvadd_fw.S delete mode 100644 isa/rv64uv/vvadd_packed.S delete mode 100644 isa/rv64uv/vvadd_w.S delete mode 100644 isa/rv64uv/vvmul_d.S delete mode 100644 isa/rv64uv/wakeup.S diff --git a/benchmarks/Makefile b/benchmarks/Makefile index 9738f61..2b71b50 100644 --- a/benchmarks/Makefile +++ b/benchmarks/Makefile @@ -27,10 +27,6 @@ bmarks = \ spmv \ mt-vvadd \ mt-matmul \ - #vec-fft \ - #vec-vvadd \ - #vec-cmplxmult \ - #vec-matmul \ bmarks_host = \ median \ @@ -52,7 +48,7 @@ HOST_COMP = gcc $(HOST_OPTS) RISCV_PREFIX=riscv64-unknown-elf- RISCV_GCC = $(RISCV_PREFIX)gcc -RISCV_GCC_OPTS = -static -Wa,-march=RVIMAFDXhwacha -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf +RISCV_GCC_OPTS = -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf RISCV_LINK = $(RISCV_GCC) -T $(bmarkdir)/common/test.ld $(incs) RISCV_LINK_MT = $(RISCV_GCC) -T $(bmarkdir)/common/test-mt.ld RISCV_LINK_OPTS = -nostdlib -nostartfiles -ffast-math -lc -lgcc diff --git a/benchmarks/mm/bmark.mk b/benchmarks/mm/bmark.mk index bb982a8..ec8fd16 100644 --- a/benchmarks/mm/bmark.mk +++ b/benchmarks/mm/bmark.mk @@ -14,7 +14,6 @@ mm_c_src = \ syscalls.c \ mm_riscv_src = \ - hwacha.S \ crt.S \ mm_c_objs = $(patsubst %.c, %.o, $(mm_c_src)) diff --git a/benchmarks/mm/common.h b/benchmarks/mm/common.h index c48cc57..01b9f3f 100644 --- a/benchmarks/mm/common.h +++ b/benchmarks/mm/common.h @@ -19,7 +19,6 @@ typedef double t; #define alloca_aligned(s, a) ((void*)(((uintptr_t)alloca((s)+(a)-1)+(a)-1)&~((a)-1))) #include "rb.h" -#include "hwacha.h" #ifdef __cplusplus extern "C" { diff --git a/benchmarks/mm/hwacha.S b/benchmarks/mm/hwacha.S deleted file mode 100644 index e5a67b4..0000000 --- a/benchmarks/mm/hwacha.S +++ /dev/null @@ -1,94 +0,0 @@ -# See LICENSE for license details. - - .text - .align 2 - - .globl hwacha_mm_0 -hwacha_mm_0: - fmadd.d f0,f19,f20,f0 - stop - - .globl hwacha_mm_1 -hwacha_mm_1: - fmadd.d f1,f18,f20,f1 - stop - - .globl hwacha_mm_2 -hwacha_mm_2: - fmadd.d f2,f19,f20,f2 - stop - - .globl hwacha_mm_3 -hwacha_mm_3: - fmadd.d f3,f18,f20,f3 - stop - - .globl hwacha_mm_4 -hwacha_mm_4: - fmadd.d f4,f19,f20,f4 - stop - - .globl hwacha_mm_5 -hwacha_mm_5: - fmadd.d f5,f18,f20,f5 - stop - - .globl hwacha_mm_6 -hwacha_mm_6: - fmadd.d f6,f19,f20,f6 - stop - - .globl hwacha_mm_7 -hwacha_mm_7: - fmadd.d f7,f18,f20,f7 - stop - - .globl hwacha_mm_8 -hwacha_mm_8: - fmadd.d f8,f19,f20,f8 - stop - - .globl hwacha_mm_9 -hwacha_mm_9: - fmadd.d f9,f18,f20,f9 - stop - - .globl hwacha_mm_10 -hwacha_mm_10: - fmadd.d f10,f19,f20,f10 - stop - - .globl hwacha_mm_11 -hwacha_mm_11: - fmadd.d f11,f18,f20,f11 - stop - - .globl hwacha_mm_12 -hwacha_mm_12: - fmadd.d f12,f19,f20,f12 - stop - - .globl hwacha_mm_13 -hwacha_mm_13: - fmadd.d f13,f18,f20,f13 - stop - - .globl hwacha_mm_14 -hwacha_mm_14: - fmadd.d f14,f19,f20,f14 - stop - - .globl hwacha_mm_15 -hwacha_mm_15: - fmadd.d f15,f18,f20,f15 - stop - - .globl hwacha_mm_16 -hwacha_mm_16: - fmadd.d f16,f19,f20,f16 - stop - - .globl hwacha_mm_17 -hwacha_mm_17: - fmadd.d f17,f18,f20,f17 - stop diff --git a/benchmarks/mm/hwacha.h b/benchmarks/mm/hwacha.h deleted file mode 100644 index 42abc87..0000000 --- a/benchmarks/mm/hwacha.h +++ /dev/null @@ -1,140 +0,0 @@ -// See LICENSE for license details. - -static const int HCBM = 18; -static const int HCBN = 80; -static const int HCBK = 16; - -static const int HRBM = 18; -static const int HRBN = 80; -static const int HRBK = 1; - -extern void hwacha_mm_0(); -extern void hwacha_mm_1(); -extern void hwacha_mm_2(); -extern void hwacha_mm_3(); -extern void hwacha_mm_4(); -extern void hwacha_mm_5(); -extern void hwacha_mm_6(); -extern void hwacha_mm_7(); -extern void hwacha_mm_8(); -extern void hwacha_mm_9(); -extern void hwacha_mm_10(); -extern void hwacha_mm_11(); -extern void hwacha_mm_12(); -extern void hwacha_mm_13(); -extern void hwacha_mm_14(); -extern void hwacha_mm_15(); -extern void hwacha_mm_16(); -extern void hwacha_mm_17(); - -static inline void nloop(int s, int e, t* a, size_t lda, t* b, size_t ldb, t* c, size_t ldc) -{ - asm volatile ("vfmsv.d vf19, %[ptr]" : : [ptr]"r"(a[0*lda])); - asm volatile ("vfld vf20, %[ptr]" : : [ptr]"r"(b) : ); - if (s) asm volatile ("vfld vf0, %[ptr]" : : [ptr]"r"(&c[ldc*0]) : ); - asm volatile ("vf 0(%[vf_ptr])" : : [vf_ptr]"r"(&hwacha_mm_0) : ); - if (e) asm volatile ("vfsd vf0, %[ptr]" : : [ptr]"r"(&c[ldc*0]) : ); - - asm volatile ("vfmsv.d vf18, %[ptr]" : : [ptr]"r"(a[1*lda])); - if (s) asm volatile ("vfld vf1, %[ptr]" : : [ptr]"r"(&c[ldc*1]) : ); - asm volatile ("vf 0(%[vf_ptr])" : : [vf_ptr]"r"(&hwacha_mm_1) : ); - if (e) asm volatile ("vfsd vf1, %[ptr]" : : [ptr]"r"(&c[ldc*1]) : ); - - asm volatile ("vfmsv.d vf19, %[ptr]" : : [ptr]"r"(a[2*lda])); - if (s) asm volatile ("vfld vf2, %[ptr]" : : [ptr]"r"(&c[ldc*2]) : ); - asm volatile ("vf 0(%[vf_ptr])" : : [vf_ptr]"r"(&hwacha_mm_2) : ); - if (e) asm volatile ("vfsd vf2, %[ptr]" : : [ptr]"r"(&c[ldc*2]) : ); - - asm volatile ("vfmsv.d vf18, %[ptr]" : : [ptr]"r"(a[3*lda])); - if (s) asm volatile ("vfld vf3, %[ptr]" : : [ptr]"r"(&c[ldc*3]) : ); - asm volatile ("vf 0(%[vf_ptr])" : : [vf_ptr]"r"(&hwacha_mm_3) : ); - if (e) asm volatile ("vfsd vf3, %[ptr]" : : [ptr]"r"(&c[ldc*3]) : ); - - asm volatile ("vfmsv.d vf19, %[ptr]" : : [ptr]"r"(a[4*lda])); - if (s) asm volatile ("vfld vf4, %[ptr]" : : [ptr]"r"(&c[ldc*4]) : ); - asm volatile ("vf 0(%[vf_ptr])" : : [vf_ptr]"r"(&hwacha_mm_4) : ); - if (e) asm volatile ("vfsd vf4, %[ptr]" : : [ptr]"r"(&c[ldc*4]) : ); - - asm volatile ("vfmsv.d vf18, %[ptr]" : : [ptr]"r"(a[5*lda])); - if (s) asm volatile ("vfld vf5, %[ptr]" : : [ptr]"r"(&c[ldc*5]) : ); - asm volatile ("vf 0(%[vf_ptr])" : : [vf_ptr]"r"(&hwacha_mm_5) : ); - if (e) asm volatile ("vfsd vf5, %[ptr]" : : [ptr]"r"(&c[ldc*5]) : ); - - asm volatile ("vfmsv.d vf19, %[ptr]" : : [ptr]"r"(a[6*lda])); - if (s) asm volatile ("vfld vf6, %[ptr]" : : [ptr]"r"(&c[ldc*6]) : ); - asm volatile ("vf 0(%[vf_ptr])" : : [vf_ptr]"r"(&hwacha_mm_6) : ); - if (e) asm volatile ("vfsd vf6, %[ptr]" : : [ptr]"r"(&c[ldc*6]) : ); - - asm volatile ("vfmsv.d vf18, %[ptr]" : : [ptr]"r"(a[7*lda])); - if (s) asm volatile ("vfld vf7, %[ptr]" : : [ptr]"r"(&c[ldc*7]) : ); - asm volatile ("vf 0(%[vf_ptr])" : : [vf_ptr]"r"(&hwacha_mm_7) : ); - if (e) asm volatile ("vfsd vf7, %[ptr]" : : [ptr]"r"(&c[ldc*7]) : ); - - asm volatile ("vfmsv.d vf19, %[ptr]" : : [ptr]"r"(a[8*lda])); - if (s) asm volatile ("vfld vf8, %[ptr]" : : [ptr]"r"(&c[ldc*8]) : ); - asm volatile ("vf 0(%[vf_ptr])" : : [vf_ptr]"r"(&hwacha_mm_8) : ); - if (e) asm volatile ("vfsd vf8, %[ptr]" : : [ptr]"r"(&c[ldc*8]) : ); - - asm volatile ("vfmsv.d vf18, %[ptr]" : : [ptr]"r"(a[9*lda])); - if (s) asm volatile ("vfld vf9, %[ptr]" : : [ptr]"r"(&c[ldc*9]) : ); - asm volatile ("vf 0(%[vf_ptr])" : : [vf_ptr]"r"(&hwacha_mm_9) : ); - if (e) asm volatile ("vfsd vf9, %[ptr]" : : [ptr]"r"(&c[ldc*9]) : ); - - asm volatile ("vfmsv.d vf19, %[ptr]" : : [ptr]"r"(a[10*lda])); - if (s) asm volatile ("vfld vf10, %[ptr]" : : [ptr]"r"(&c[ldc*10]) : ); - asm volatile ("vf 0(%[vf_ptr])" : : [vf_ptr]"r"(&hwacha_mm_10) : ); - if (e) asm volatile ("vfsd vf10, %[ptr]" : : [ptr]"r"(&c[ldc*10]) : ); - - asm volatile ("vfmsv.d vf18, %[ptr]" : : [ptr]"r"(a[11*lda])); - if (s) asm volatile ("vfld vf11, %[ptr]" : : [ptr]"r"(&c[ldc*11]) : ); - asm volatile ("vf 0(%[vf_ptr])" : : [vf_ptr]"r"(&hwacha_mm_11) : ); - if (e) asm volatile ("vfsd vf11, %[ptr]" : : [ptr]"r"(&c[ldc*11]) : ); - - asm volatile ("vfmsv.d vf19, %[ptr]" : : [ptr]"r"(a[12*lda])); - if (s) asm volatile ("vfld vf12, %[ptr]" : : [ptr]"r"(&c[ldc*12]) : ); - asm volatile ("vf 0(%[vf_ptr])" : : [vf_ptr]"r"(&hwacha_mm_12) : ); - if (e) asm volatile ("vfsd vf12, %[ptr]" : : [ptr]"r"(&c[ldc*12]) : ); - - asm volatile ("vfmsv.d vf18, %[ptr]" : : [ptr]"r"(a[13*lda])); - if (s) asm volatile ("vfld vf13, %[ptr]" : : [ptr]"r"(&c[ldc*13]) : ); - asm volatile ("vf 0(%[vf_ptr])" : : [vf_ptr]"r"(&hwacha_mm_13) : ); - if (e) asm volatile ("vfsd vf13, %[ptr]" : : [ptr]"r"(&c[ldc*13]) : ); - - asm volatile ("vfmsv.d vf19, %[ptr]" : : [ptr]"r"(a[14*lda])); - if (s) asm volatile ("vfld vf14, %[ptr]" : : [ptr]"r"(&c[ldc*14]) : ); - asm volatile ("vf 0(%[vf_ptr])" : : [vf_ptr]"r"(&hwacha_mm_14) : ); - if (e) asm volatile ("vfsd vf14, %[ptr]" : : [ptr]"r"(&c[ldc*14]) : ); - - asm volatile ("vfmsv.d vf18, %[ptr]" : : [ptr]"r"(a[15*lda])); - if (s) asm volatile ("vfld vf15, %[ptr]" : : [ptr]"r"(&c[ldc*15]) : ); - asm volatile ("vf 0(%[vf_ptr])" : : [vf_ptr]"r"(&hwacha_mm_15) : ); - if (e) asm volatile ("vfsd vf15, %[ptr]" : : [ptr]"r"(&c[ldc*15]) : ); - - asm volatile ("vfmsv.d vf19, %[ptr]" : : [ptr]"r"(a[16*lda])); - if (s) asm volatile ("vfld vf16, %[ptr]" : : [ptr]"r"(&c[ldc*16]) : ); - asm volatile ("vf 0(%[vf_ptr])" : : [vf_ptr]"r"(&hwacha_mm_16) : ); - if (e) asm volatile ("vfsd vf16, %[ptr]" : : [ptr]"r"(&c[ldc*16]) : ); - - asm volatile ("vfmsv.d vf18, %[ptr]" : : [ptr]"r"(a[17*lda])); - if (s) asm volatile ("vfld vf17, %[ptr]" : : [ptr]"r"(&c[ldc*17]) : ); - asm volatile ("vf 0(%[vf_ptr])" : : [vf_ptr]"r"(&hwacha_mm_17) : ); - if (e) asm volatile ("vfsd vf17, %[ptr]" : : [ptr]"r"(&c[ldc*17]) : ); -} - -static inline void mm_rb_hwacha(size_t m, size_t n, size_t p, - t* a, size_t lda, t* b, size_t ldb, t* c, size_t ldc) -{ - int vl; - asm volatile ("vsetcfg 4, 21" : : : ); - asm volatile ("vsetvl %[gvl], %[nvl]" : [gvl]"=r"(vl) : [nvl]"r"(n) : ); - - size_t mb = m/HRBM*HRBM, nk=p/HRBK*HRBK; - - for (size_t i=0; i[$i], $arrayRefImag->[$i]); - if ( $i != $arrayLen-1 ) { - print ",\n "; - } - } - - print "\n};\n\n"; -} - -#-------------------------------------------------------------------------- -# Main -#-------------------------------------------------------------------------- - -sub main() -{ - - processCommandLine(); - srand($opts{"seed"}); - - my @values_real1; - my @values_imag1; - my @values_real2; - my @values_imag2; - my @product_real; - my @product_imag; - for ( my $i = 0; $i < $opts{"size"}; $i++ ) { - my $value_real1 = (rand(9.0)); - my $value_imag1 = (rand(9.0)); - my $value_real2 = (rand(9.0)); - my $value_imag2 = (rand(9.0)); - push( @values_real1, $value_real1 ); - push( @values_imag1, $value_imag1 ); - push( @values_real2, $value_real2 ); - push( @values_imag2, $value_imag2 ); - push( @product_real, ($value_real1 * $value_real2) - ($value_imag1 * $value_imag2)); - push( @product_imag, ($value_imag1 * $value_real2) + ($value_real1 * $value_imag2)); - } - - - print "\n\#define DATA_SIZE ".$opts{"size"}." \n\n"; - printArray( "input1_data", \@values_real1, \@values_imag1 ); - printArray( "input2_data", \@values_real2, \@values_imag2 ); - printArray( "verify_data", \@product_real, \@product_imag ); - -} - -main(); - diff --git a/benchmarks/vec-cmplxmult/dataset.h b/benchmarks/vec-cmplxmult/dataset.h deleted file mode 100644 index 7fb3856..0000000 --- a/benchmarks/vec-cmplxmult/dataset.h +++ /dev/null @@ -1,1553 +0,0 @@ -// See LICENSE for license details. - - -#define DATA_SIZE 512 - -struct Complex input1_data[DATA_SIZE] = -{ - {0.37, 4.09}, - {5.09, 0.02}, - {6.75, 3.30}, - {1.19, 0.58}, - {5.26, 1.95}, - {5.60, 1.90}, - {8.39, 3.06}, - {3.54, 8.09}, - {8.66, 0.11}, - {1.05, 6.76}, - {3.84, 4.51}, - {5.94, 6.32}, - {2.88, 8.84}, - {7.88, 6.27}, - {4.27, 2.45}, - {4.86, 5.83}, - {1.83, 0.80}, - {6.84, 6.04}, - {4.61, 4.97}, - {1.76, 5.34}, - {2.41, 8.58}, - {3.04, 5.26}, - {8.13, 3.32}, - {8.23, 2.96}, - {8.41, 5.34}, - {1.77, 4.90}, - {5.11, 8.82}, - {5.85, 7.34}, - {1.63, 1.88}, - {7.74, 5.67}, - {2.60, 6.35}, - {1.28, 2.28}, - {7.98, 3.87}, - {5.20, 4.85}, - {6.86, 0.04}, - {4.31, 0.90}, - {3.63, 6.25}, - {4.00, 2.67}, - {6.09, 5.59}, - {2.02, 3.17}, - {2.60, 5.83}, - {5.54, 4.75}, - {3.51, 7.17}, - {4.10, 6.49}, - {3.31, 6.72}, - {5.26, 8.91}, - {8.88, 7.69}, - {3.12, 4.79}, - {5.04, 4.15}, - {6.99, 3.23}, - {7.02, 6.17}, - {1.29, 4.02}, - {1.13, 6.70}, - {8.41, 4.32}, - {4.98, 8.34}, - {5.85, 3.22}, - {2.59, 6.00}, - {0.45, 5.03}, - {0.86, 7.69}, - {5.29, 0.55}, - {3.44, 3.57}, - {7.28, 0.16}, - {7.38, 2.62}, - {4.06, 4.83}, - {8.70, 8.26}, - {7.29, 8.86}, - {4.84, 0.49}, - {6.32, 8.57}, - {5.12, 1.36}, - {0.20, 5.78}, - {6.00, 6.58}, - {3.91, 6.56}, - {0.02, 3.56}, - {2.23, 8.21}, - {3.92, 7.34}, - {7.83, 2.39}, - {3.73, 2.13}, - {4.94, 1.63}, - {8.00, 4.54}, - {2.57, 1.56}, - {4.50, 3.13}, - {8.08, 0.62}, - {6.59, 5.93}, - {2.26, 1.10}, - {5.01, 7.47}, - {4.76, 3.91}, - {2.90, 6.79}, - {2.59, 5.65}, - {2.75, 0.10}, - {6.61, 0.95}, - {3.30, 7.37}, - {2.65, 3.66}, - {5.89, 7.72}, - {0.82, 0.54}, - {0.95, 6.02}, - {3.44, 1.09}, - {7.44, 3.72}, - {3.22, 0.11}, - {0.49, 8.70}, - {8.61, 5.60}, - {4.81, 8.30}, - {4.70, 5.83}, - {5.34, 7.99}, - {1.56, 0.33}, - {1.09, 4.96}, - {6.83, 8.74}, - {8.57, 3.91}, - {1.17, 2.73}, - {7.64, 7.75}, - {2.30, 4.31}, - {3.69, 6.08}, - {3.60, 8.92}, - {6.79, 4.06}, - {1.54, 1.40}, - {6.55, 4.08}, - {7.01, 4.59}, - {6.79, 3.84}, - {1.82, 4.35}, - {1.39, 3.06}, - {3.22, 0.46}, - {8.31, 5.42}, - {4.47, 8.73}, - {4.66, 7.93}, - {2.49, 7.84}, - {1.03, 5.44}, - {8.17, 8.00}, - {2.14, 3.65}, - {7.07, 6.72}, - {3.22, 2.48}, - {7.38, 2.04}, - {2.52, 8.50}, - {4.13, 6.39}, - {6.40, 0.49}, - {0.38, 0.48}, - {3.40, 0.37}, - {6.31, 3.75}, - {4.33, 1.98}, - {4.50, 6.94}, - {0.45, 4.35}, - {7.87, 6.53}, - {8.94, 1.68}, - {6.50, 0.01}, - {2.10, 2.23}, - {6.29, 3.27}, - {3.14, 2.11}, - {3.16, 0.37}, - {5.17, 1.76}, - {6.75, 6.70}, - {7.42, 3.21}, - {1.53, 1.27}, - {6.08, 2.61}, - {1.82, 2.88}, - {7.69, 1.07}, - {3.56, 0.64}, - {7.70, 3.50}, - {1.42, 0.32}, - {6.90, 6.29}, - {1.76, 6.10}, - {1.97, 7.96}, - {1.60, 6.73}, - {6.30, 4.61}, - {6.37, 3.97}, - {0.76, 6.60}, - {8.05, 6.33}, - {3.36, 0.78}, - {0.13, 1.94}, - {0.75, 5.87}, - {7.16, 3.87}, - {5.79, 0.87}, - {7.52, 5.94}, - {4.16, 4.72}, - {5.06, 5.63}, - {0.09, 6.44}, - {8.15, 0.50}, - {3.67, 2.75}, - {5.04, 8.12}, - {4.62, 6.23}, - {2.73, 4.48}, - {3.85, 8.48}, - {3.24, 4.33}, - {6.17, 7.41}, - {1.67, 6.13}, - {0.97, 1.01}, - {3.49, 1.67}, - {4.38, 6.48}, - {6.30, 6.75}, - {6.94, 7.33}, - {0.73, 2.94}, - {3.67, 0.31}, - {0.27, 8.43}, - {7.84, 0.80}, - {1.34, 3.06}, - {1.33, 4.99}, - {7.61, 8.60}, - {1.27, 3.57}, - {7.36, 2.25}, - {5.07, 7.50}, - {5.55, 3.55}, - {7.32, 4.24}, - {1.44, 3.03}, - {7.24, 2.25}, - {4.91, 4.89}, - {4.13, 5.73}, - {7.86, 5.24}, - {7.26, 6.05}, - {0.94, 3.77}, - {2.29, 8.29}, - {1.23, 6.71}, - {5.27, 1.25}, - {3.74, 8.36}, - {6.37, 4.12}, - {3.41, 1.66}, - {8.80, 1.77}, - {8.54, 3.75}, - {1.49, 8.98}, - {0.95, 6.63}, - {7.17, 7.44}, - {2.74, 0.46}, - {5.72, 4.84}, - {1.07, 2.65}, - {4.79, 0.99}, - {0.34, 7.04}, - {6.67, 3.38}, - {6.91, 8.08}, - {0.52, 0.40}, - {7.07, 7.62}, - {7.54, 0.89}, - {0.61, 4.00}, - {8.98, 1.49}, - {1.55, 0.26}, - {5.60, 2.92}, - {7.44, 3.39}, - {6.25, 8.09}, - {2.13, 1.52}, - {6.71, 1.75}, - {1.12, 8.43}, - {8.49, 7.04}, - {3.34, 5.58}, - {2.43, 8.41}, - {6.88, 7.45}, - {8.25, 8.90}, - {0.01, 5.85}, - {8.97, 0.01}, - {5.05, 3.60}, - {8.76, 7.13}, - {4.59, 8.87}, - {8.74, 5.41}, - {5.22, 6.15}, - {2.26, 8.14}, - {1.16, 8.97}, - {6.45, 5.61}, - {6.12, 8.07}, - {2.17, 7.39}, - {7.15, 2.04}, - {0.01, 2.37}, - {8.89, 2.15}, - {6.80, 5.50}, - {1.83, 2.15}, - {1.62, 7.97}, - {1.49, 0.97}, - {8.78, 7.11}, - {5.04, 0.21}, - {3.81, 8.02}, - {5.10, 0.48}, - {4.44, 1.81}, - {6.72, 3.68}, - {3.36, 5.82}, - {5.99, 0.74}, - {4.81, 0.47}, - {8.19, 2.02}, - {0.30, 6.63}, - {3.30, 1.51}, - {7.04, 4.79}, - {6.35, 1.52}, - {8.53, 0.92}, - {0.45, 0.39}, - {4.28, 5.90}, - {6.12, 5.64}, - {8.59, 7.41}, - {4.30, 5.78}, - {6.43, 2.21}, - {4.77, 7.90}, - {0.70, 5.41}, - {8.18, 6.98}, - {1.29, 2.11}, - {2.16, 4.09}, - {3.29, 1.89}, - {0.49, 8.12}, - {3.96, 5.91}, - {2.84, 5.36}, - {6.28, 4.19}, - {6.54, 0.63}, - {2.55, 0.29}, - {5.61, 0.23}, - {8.02, 4.40}, - {2.62, 3.69}, - {6.54, 0.25}, - {4.94, 4.86}, - {5.81, 2.73}, - {2.61, 6.62}, - {1.47, 4.98}, - {4.43, 0.97}, - {1.05, 0.44}, - {7.74, 1.30}, - {2.55, 6.53}, - {8.23, 4.24}, - {1.76, 3.09}, - {7.05, 6.10}, - {6.56, 3.03}, - {3.88, 4.19}, - {6.85, 5.32}, - {2.79, 3.66}, - {3.19, 6.72}, - {6.30, 4.73}, - {4.39, 2.31}, - {0.91, 4.92}, - {2.42, 3.31}, - {0.68, 0.96}, - {8.90, 3.57}, - {8.19, 3.87}, - {0.83, 1.18}, - {2.50, 8.93}, - {3.17, 8.93}, - {7.78, 4.05}, - {0.91, 5.55}, - {5.12, 6.37}, - {3.34, 7.63}, - {4.16, 2.85}, - {1.64, 6.72}, - {1.44, 4.71}, - {0.20, 1.04}, - {5.81, 2.04}, - {7.02, 1.80}, - {7.71, 6.69}, - {8.86, 6.35}, - {5.09, 7.07}, - {2.28, 8.67}, - {1.39, 2.65}, - {2.29, 1.30}, - {8.10, 7.17}, - {2.94, 6.11}, - {2.78, 7.15}, - {1.44, 5.74}, - {7.56, 2.18}, - {4.96, 6.24}, - {0.74, 5.42}, - {2.92, 3.59}, - {0.93, 0.66}, - {8.71, 8.81}, - {1.60, 5.03}, - {3.36, 4.56}, - {5.40, 5.87}, - {3.40, 2.89}, - {5.33, 3.61}, - {3.97, 7.61}, - {5.35, 8.41}, - {8.18, 4.04}, - {3.40, 0.46}, - {7.04, 8.11}, - {4.47, 6.74}, - {7.27, 0.06}, - {4.94, 2.57}, - {0.27, 4.06}, - {5.68, 6.95}, - {5.53, 4.82}, - {1.05, 4.34}, - {8.15, 3.91}, - {5.47, 0.38}, - {1.53, 7.80}, - {4.57, 3.74}, - {3.89, 4.86}, - {1.33, 0.95}, - {1.01, 5.36}, - {7.52, 3.15}, - {8.55, 2.59}, - {4.40, 1.39}, - {7.19, 4.86}, - {6.93, 7.86}, - {4.37, 5.88}, - {6.50, 6.74}, - {7.40, 3.07}, - {0.00, 1.86}, - {2.50, 4.56}, - {6.13, 8.66}, - {5.00, 5.65}, - {4.66, 8.75}, - {4.56, 3.70}, - {2.22, 0.57}, - {3.55, 3.57}, - {1.93, 5.58}, - {4.73, 5.02}, - {1.56, 0.61}, - {5.59, 4.62}, - {4.82, 0.06}, - {1.44, 7.95}, - {7.30, 6.89}, - {0.68, 4.56}, - {1.51, 7.49}, - {7.69, 5.75}, - {2.92, 0.66}, - {0.47, 0.54}, - {0.10, 8.37}, - {6.58, 8.66}, - {2.59, 7.19}, - {0.83, 7.69}, - {8.22, 5.41}, - {7.75, 2.10}, - {6.71, 1.62}, - {5.54, 6.22}, - {8.24, 4.46}, - {2.60, 2.11}, - {1.16, 7.03}, - {4.95, 0.20}, - {8.84, 6.68}, - {5.61, 3.86}, - {5.64, 5.44}, - {3.48, 3.11}, - {4.26, 2.86}, - {2.16, 7.76}, - {7.79, 4.61}, - {3.21, 0.63}, - {7.44, 7.69}, - {3.52, 4.42}, - {0.35, 2.73}, - {5.56, 7.33}, - {1.86, 3.50}, - {7.06, 8.72}, - {7.34, 0.44}, - {6.00, 2.27}, - {0.85, 6.68}, - {3.80, 1.59}, - {6.08, 4.72}, - {3.37, 8.58}, - {0.58, 4.79}, - {6.83, 0.21}, - {4.51, 7.63}, - {3.03, 7.70}, - {2.14, 0.22}, - {4.22, 2.87}, - {5.09, 5.97}, - {4.05, 2.53}, - {1.23, 2.65}, - {3.45, 6.61}, - {2.42, 4.24}, - {8.18, 6.07}, - {8.58, 3.96}, - {3.58, 1.40}, - {2.09, 8.55}, - {0.32, 4.01}, - {3.99, 7.07}, - {3.50, 8.50}, - {5.60, 3.30}, - {5.52, 5.45}, - {8.59, 3.07}, - {4.16, 8.21}, - {7.32, 3.92}, - {6.06, 0.71}, - {2.82, 8.56}, - {0.50, 0.24}, - {6.79, 1.81}, - {7.92, 7.91}, - {5.16, 7.92}, - {6.50, 1.29}, - {5.80, 7.32}, - {8.72, 4.75}, - {7.57, 7.18}, - {5.68, 2.65}, - {7.16, 2.49}, - {7.98, 3.72}, - {6.28, 3.48}, - {0.84, 2.91}, - {7.07, 4.85}, - {5.24, 8.65}, - {8.32, 0.44}, - {5.88, 8.09}, - {2.36, 4.46}, - {5.49, 7.25}, - {4.86, 3.89}, - {5.05, 1.73}, - {0.18, 7.01}, - {8.80, 3.24}, - {3.48, 6.73}, - {5.98, 6.75}, - {1.91, 3.68}, - {8.17, 3.98}, - {6.64, 0.88}, - {0.23, 3.24}, - {7.19, 6.06}, - {4.07, 7.93}, - {6.16, 2.71}, - {7.35, 8.32}, - {5.52, 7.36}, - {1.05, 2.20}, - {2.54, 8.26}, - {2.61, 5.89}, - {5.81, 3.66}, - {8.40, 0.98}, - {6.17, 4.18}, - {7.89, 0.78}, - {3.71, 4.02}, - {5.98, 4.86}, - {7.06, 0.26}, - {6.38, 6.63}, - {4.72, 5.50}, - {0.34, 6.06}, - {0.39, 6.90}, - {1.12, 3.69}, - {7.34, 1.68}, - {1.93, 5.12}, - {5.16, 8.99}, - {8.62, 4.11}, - {5.87, 5.10} -}; - -struct Complex input2_data[DATA_SIZE] = -{ - {7.51, 3.02}, - {1.69, 8.91}, - {3.16, 5.16}, - {8.56, 1.38}, - {7.26, 1.26}, - {0.06, 5.16}, - {8.02, 5.34}, - {6.25, 2.06}, - {1.00, 7.96}, - {2.67, 5.82}, - {2.83, 3.93}, - {6.97, 7.32}, - {6.12, 1.36}, - {3.40, 5.08}, - {8.45, 2.33}, - {5.13, 4.59}, - {2.53, 6.34}, - {5.46, 3.38}, - {5.93, 8.44}, - {0.74, 5.13}, - {2.06, 7.22}, - {8.51, 5.79}, - {2.18, 4.41}, - {7.45, 2.82}, - {8.88, 3.50}, - {8.65, 5.85}, - {3.16, 8.99}, - {5.92, 0.71}, - {1.01, 8.99}, - {0.59, 7.63}, - {3.15, 8.98}, - {8.16, 6.45}, - {2.38, 3.74}, - {8.83, 6.31}, - {2.17, 4.46}, - {4.50, 7.79}, - {2.00, 3.75}, - {6.50, 2.58}, - {2.86, 0.71}, - {8.45, 4.87}, - {1.08, 1.53}, - {5.46, 2.61}, - {3.16, 7.22}, - {2.51, 6.84}, - {3.23, 0.83}, - {0.57, 2.44}, - {3.63, 7.10}, - {4.66, 2.01}, - {8.18, 2.18}, - {2.30, 2.99}, - {5.39, 6.67}, - {0.31, 2.81}, - {8.48, 5.02}, - {7.20, 5.02}, - {3.89, 7.17}, - {8.58, 8.03}, - {0.18, 4.64}, - {0.78, 7.84}, - {3.98, 3.97}, - {5.54, 6.12}, - {2.53, 0.09}, - {8.75, 1.54}, - {3.11, 3.43}, - {4.62, 1.67}, - {3.13, 4.86}, - {7.95, 8.00}, - {8.53, 5.52}, - {3.21, 4.32}, - {8.03, 0.07}, - {5.12, 3.02}, - {3.81, 0.86}, - {1.43, 2.53}, - {0.76, 6.20}, - {0.45, 4.30}, - {7.14, 6.57}, - {4.38, 1.15}, - {3.33, 1.93}, - {4.67, 0.06}, - {6.15, 5.37}, - {2.38, 5.80}, - {2.62, 5.40}, - {1.94, 7.66}, - {6.20, 5.58}, - {7.08, 1.19}, - {2.72, 6.01}, - {4.91, 4.40}, - {8.54, 1.13}, - {7.42, 0.13}, - {7.11, 3.64}, - {8.65, 6.34}, - {6.51, 8.69}, - {8.79, 7.88}, - {6.75, 0.78}, - {3.41, 5.95}, - {0.93, 1.38}, - {5.87, 0.88}, - {7.57, 2.13}, - {1.34, 3.82}, - {1.26, 1.95}, - {3.09, 3.26}, - {6.82, 6.44}, - {7.55, 2.70}, - {0.12, 6.15}, - {0.57, 4.45}, - {1.20, 4.84}, - {3.35, 5.79}, - {0.36, 3.74}, - {1.00, 3.95}, - {3.94, 1.83}, - {2.43, 8.90}, - {5.66, 6.48}, - {4.95, 3.05}, - {5.08, 5.70}, - {0.17, 5.83}, - {4.52, 3.85}, - {0.39, 8.91}, - {0.73, 0.11}, - {7.69, 1.28}, - {6.85, 3.52}, - {8.50, 1.54}, - {2.96, 0.95}, - {3.99, 1.09}, - {5.78, 0.74}, - {7.08, 5.41}, - {7.59, 7.85}, - {2.48, 5.50}, - {0.30, 2.11}, - {5.09, 4.74}, - {7.24, 3.98}, - {6.77, 6.78}, - {0.77, 6.54}, - {4.10, 1.81}, - {4.14, 6.83}, - {2.28, 3.58}, - {4.58, 1.27}, - {7.75, 6.74}, - {6.68, 4.31}, - {6.39, 1.62}, - {3.35, 6.23}, - {8.52, 1.56}, - {4.75, 8.24}, - {3.92, 8.68}, - {4.48, 4.19}, - {0.28, 4.70}, - {2.26, 1.09}, - {2.26, 7.02}, - {7.06, 1.45}, - {4.53, 3.96}, - {7.45, 3.63}, - {1.45, 5.70}, - {0.29, 7.05}, - {1.29, 5.73}, - {0.81, 7.68}, - {0.97, 7.35}, - {0.96, 8.60}, - {0.05, 0.15}, - {1.84, 6.27}, - {5.18, 5.39}, - {4.74, 7.43}, - {2.16, 4.17}, - {6.82, 4.81}, - {0.45, 3.86}, - {7.21, 6.55}, - {4.62, 4.93}, - {4.44, 7.20}, - {5.60, 0.20}, - {0.93, 0.54}, - {8.30, 5.93}, - {7.93, 8.77}, - {2.16, 8.70}, - {1.03, 0.56}, - {4.77, 2.73}, - {8.98, 3.69}, - {3.49, 6.57}, - {0.95, 3.93}, - {8.44, 5.34}, - {3.69, 7.18}, - {1.82, 1.60}, - {5.53, 8.97}, - {4.70, 1.43}, - {0.20, 5.51}, - {2.82, 0.13}, - {2.48, 7.18}, - {2.19, 0.00}, - {0.95, 0.87}, - {8.10, 6.66}, - {5.81, 3.92}, - {1.46, 0.34}, - {8.52, 5.46}, - {6.92, 0.24}, - {1.03, 3.98}, - {0.56, 3.10}, - {7.55, 3.29}, - {3.90, 5.76}, - {1.90, 8.93}, - {7.40, 3.05}, - {3.28, 8.78}, - {4.47, 2.40}, - {8.26, 3.14}, - {3.88, 3.78}, - {1.62, 1.95}, - {7.57, 8.14}, - {7.09, 6.58}, - {7.17, 7.39}, - {6.83, 8.82}, - {3.62, 6.04}, - {8.87, 5.12}, - {6.57, 5.97}, - {7.16, 3.48}, - {4.76, 1.56}, - {4.99, 2.85}, - {6.91, 4.30}, - {2.13, 3.60}, - {2.07, 7.26}, - {4.56, 2.43}, - {6.35, 6.28}, - {1.26, 4.76}, - {7.17, 5.62}, - {5.05, 0.79}, - {0.08, 7.82}, - {7.33, 3.59}, - {5.27, 5.83}, - {5.58, 8.50}, - {4.31, 5.31}, - {8.64, 2.60}, - {8.88, 6.69}, - {2.77, 4.71}, - {7.43, 3.89}, - {6.75, 8.39}, - {7.44, 4.16}, - {1.40, 2.46}, - {0.39, 3.07}, - {0.73, 1.43}, - {6.74, 4.00}, - {2.40, 5.69}, - {6.59, 2.47}, - {3.83, 1.67}, - {2.89, 2.63}, - {4.89, 1.41}, - {6.78, 0.80}, - {0.13, 5.67}, - {8.16, 0.29}, - {7.30, 6.71}, - {7.87, 8.25}, - {2.61, 5.00}, - {5.03, 4.78}, - {3.65, 3.62}, - {2.64, 4.87}, - {7.66, 1.09}, - {4.08, 4.70}, - {0.78, 2.02}, - {1.64, 4.78}, - {3.03, 5.87}, - {5.78, 0.87}, - {2.88, 5.13}, - {5.83, 1.14}, - {8.64, 1.73}, - {1.28, 7.18}, - {2.70, 5.16}, - {6.86, 1.27}, - {5.83, 7.68}, - {5.58, 6.35}, - {2.35, 4.33}, - {4.88, 3.36}, - {8.93, 4.92}, - {1.87, 1.08}, - {8.40, 4.19}, - {0.31, 2.64}, - {4.31, 7.93}, - {1.83, 6.71}, - {1.93, 7.98}, - {8.04, 0.02}, - {6.13, 2.90}, - {6.20, 4.38}, - {3.48, 1.60}, - {0.91, 6.38}, - {3.60, 8.25}, - {2.97, 2.18}, - {4.25, 7.17}, - {6.54, 2.27}, - {8.45, 1.36}, - {7.84, 3.00}, - {4.91, 8.46}, - {7.69, 3.58}, - {8.82, 6.81}, - {0.95, 3.82}, - {0.89, 8.67}, - {0.88, 8.32}, - {6.89, 4.77}, - {3.03, 0.82}, - {6.98, 6.18}, - {2.92, 6.80}, - {4.83, 4.46}, - {5.36, 3.51}, - {0.68, 0.34}, - {4.47, 5.76}, - {4.05, 8.57}, - {1.22, 0.73}, - {7.55, 6.52}, - {6.91, 1.13}, - {3.75, 2.24}, - {8.88, 3.26}, - {5.57, 7.83}, - {2.12, 7.58}, - {5.15, 3.02}, - {5.05, 2.37}, - {2.18, 7.29}, - {8.88, 3.06}, - {3.10, 3.70}, - {5.52, 0.51}, - {1.59, 4.38}, - {3.01, 8.95}, - {2.79, 2.15}, - {0.42, 3.03}, - {4.54, 1.21}, - {3.54, 6.51}, - {2.83, 8.50}, - {3.12, 5.67}, - {5.41, 1.88}, - {3.47, 4.72}, - {4.91, 3.21}, - {6.02, 6.07}, - {7.69, 6.49}, - {2.82, 0.77}, - {4.80, 1.90}, - {7.53, 6.64}, - {8.92, 4.08}, - {8.22, 8.78}, - {2.42, 7.18}, - {6.95, 5.57}, - {7.70, 6.55}, - {0.16, 1.49}, - {8.21, 7.48}, - {1.24, 1.69}, - {6.46, 6.05}, - {6.48, 7.98}, - {7.08, 5.93}, - {1.77, 5.59}, - {4.03, 1.56}, - {0.05, 0.65}, - {5.55, 0.72}, - {1.58, 6.17}, - {1.11, 8.72}, - {6.45, 8.09}, - {2.07, 3.36}, - {5.65, 6.50}, - {8.35, 4.98}, - {0.16, 1.58}, - {1.43, 2.93}, - {5.35, 1.67}, - {3.55, 7.75}, - {6.72, 5.17}, - {7.80, 3.15}, - {4.98, 8.02}, - {3.12, 7.97}, - {2.62, 8.84}, - {4.91, 8.91}, - {4.11, 2.99}, - {0.99, 6.46}, - {8.07, 4.00}, - {6.31, 3.55}, - {3.07, 6.34}, - {7.48, 5.88}, - {4.92, 4.37}, - {8.76, 5.04}, - {2.83, 4.57}, - {8.75, 3.10}, - {7.16, 7.07}, - {8.08, 3.80}, - {8.26, 7.85}, - {3.06, 1.46}, - {2.03, 4.34}, - {5.23, 1.04}, - {1.21, 8.69}, - {1.82, 2.10}, - {3.57, 5.43}, - {4.31, 8.50}, - {5.17, 1.09}, - {3.06, 7.31}, - {4.06, 3.26}, - {6.71, 8.20}, - {5.36, 5.16}, - {1.08, 8.77}, - {6.82, 3.20}, - {7.64, 7.66}, - {3.42, 8.21}, - {8.15, 6.94}, - {2.19, 7.88}, - {3.88, 4.35}, - {2.20, 5.82}, - {3.60, 2.96}, - {2.75, 7.97}, - {5.36, 8.76}, - {6.30, 4.62}, - {6.76, 5.07}, - {4.10, 3.30}, - {0.84, 7.09}, - {0.15, 3.45}, - {4.46, 4.08}, - {0.71, 0.76}, - {1.01, 8.40}, - {3.09, 8.33}, - {6.13, 0.62}, - {8.66, 8.88}, - {5.64, 7.97}, - {5.55, 3.51}, - {6.70, 7.15}, - {4.31, 6.97}, - {4.58, 6.99}, - {7.30, 1.26}, - {8.78, 3.89}, - {5.23, 3.35}, - {7.82, 5.89}, - {2.43, 7.35}, - {5.88, 1.26}, - {8.92, 2.84}, - {2.92, 8.01}, - {1.48, 2.34}, - {1.71, 3.40}, - {2.09, 2.74}, - {1.38, 0.32}, - {2.96, 5.20}, - {7.64, 2.94}, - {3.63, 3.88}, - {4.92, 6.39}, - {0.02, 8.67}, - {8.02, 3.99}, - {7.50, 7.49}, - {3.70, 2.90}, - {2.22, 1.62}, - {1.91, 1.05}, - {0.09, 6.89}, - {3.85, 6.35}, - {0.48, 7.25}, - {7.31, 5.51}, - {3.95, 3.38}, - {2.96, 8.75}, - {3.75, 5.76}, - {6.17, 6.52}, - {2.75, 5.83}, - {5.39, 1.43}, - {7.95, 7.98}, - {8.45, 7.81}, - {1.04, 2.67}, - {0.45, 4.26}, - {3.30, 0.05}, - {2.32, 4.57}, - {6.01, 5.41}, - {8.93, 2.00}, - {1.93, 3.15}, - {0.12, 1.35}, - {0.48, 4.00}, - {8.42, 6.49}, - {7.47, 8.76}, - {5.60, 2.90}, - {4.71, 0.45}, - {0.52, 6.86}, - {3.18, 2.15}, - {8.76, 2.04}, - {3.75, 1.59}, - {7.79, 4.06}, - {1.47, 0.90}, - {0.11, 0.29}, - {4.57, 6.95}, - {7.04, 4.40}, - {2.18, 1.75}, - {7.30, 8.71}, - {3.93, 3.11}, - {5.40, 1.78}, - {5.80, 1.05}, - {6.40, 6.13}, - {1.01, 4.99}, - {0.12, 7.88}, - {5.55, 4.57}, - {3.24, 4.86}, - {2.10, 6.88}, - {6.18, 2.58}, - {1.06, 7.54}, - {6.66, 7.44}, - {2.86, 5.28}, - {5.17, 3.18}, - {6.96, 0.10}, - {4.55, 0.05}, - {8.01, 5.80}, - {3.79, 3.32}, - {4.65, 1.53}, - {1.98, 4.75}, - {6.46, 0.63}, - {6.23, 2.69}, - {4.14, 2.95}, - {2.92, 7.47}, - {2.23, 4.48}, - {3.18, 8.84}, - {6.66, 6.43}, - {8.20, 4.54}, - {5.64, 4.90}, - {1.98, 2.74}, - {3.36, 8.60}, - {5.83, 7.23}, - {8.61, 0.25}, - {7.66, 5.90}, - {3.54, 4.24}, - {3.80, 8.48}, - {6.15, 4.07}, - {1.41, 2.14}, - {6.92, 6.43}, - {4.95, 7.83}, - {2.26, 4.29}, - {1.91, 0.40}, - {8.10, 1.26}, - {5.49, 4.23}, - {3.92, 3.68} -}; - -struct Complex verify_data[DATA_SIZE] = -{ - {-9.55, 31.87}, - {8.45, 45.39}, - {4.34, 45.27}, - {9.41, 6.59}, - {35.73, 20.80}, - {-9.46, 29.00}, - {50.95, 69.43}, - {5.47, 57.90}, - {7.79, 69.03}, - {-36.53, 24.18}, - {-6.85, 27.86}, - {-4.86, 87.57}, - {5.59, 57.99}, - {-5.10, 61.38}, - {30.42, 30.70}, - {-1.81, 52.19}, - {-0.43, 13.62}, - {16.97, 56.10}, - {-14.63, 68.37}, - {-26.08, 12.95}, - {-56.93, 35.07}, - {-4.61, 62.42}, - {3.10, 43.03}, - {52.89, 45.25}, - {55.98, 76.85}, - {-13.41, 52.73}, - {-63.15, 73.78}, - {29.38, 47.60}, - {-15.25, 16.57}, - {-38.76, 62.42}, - {-48.83, 43.31}, - {-4.32, 26.85}, - {4.49, 39.11}, - {15.24, 75.60}, - {14.71, 30.66}, - {12.39, 37.66}, - {-16.19, 26.14}, - {19.10, 27.68}, - {13.49, 20.33}, - {1.62, 36.60}, - {-6.13, 10.25}, - {17.87, 40.40}, - {-40.70, 48.05}, - {-34.10, 44.30}, - {5.13, 24.45}, - {-18.80, 17.91}, - {-22.36, 91.00}, - {4.95, 28.61}, - {32.18, 44.95}, - {6.40, 28.33}, - {-3.28, 80.04}, - {-10.91, 4.86}, - {-24.07, 62.47}, - {38.92, 73.33}, - {-40.44, 68.15}, - {24.28, 74.58}, - {-27.37, 13.08}, - {-39.05, 7.43}, - {-27.07, 33.97}, - {25.94, 35.40}, - {8.40, 9.34}, - {63.51, 12.56}, - {13.94, 33.44}, - {10.67, 29.11}, - {-12.93, 68.17}, - {-12.91, 128.67}, - {38.58, 30.92}, - {-16.80, 54.81}, - {41.01, 11.31}, - {-16.46, 30.20}, - {17.23, 30.21}, - {-10.98, 19.28}, - {-22.07, 2.83}, - {-34.27, 13.24}, - {-20.25, 78.23}, - {31.56, 19.48}, - {8.30, 14.29}, - {22.98, 7.89}, - {24.83, 70.87}, - {-2.96, 18.61}, - {-5.10, 32.50}, - {10.92, 63.09}, - {7.76, 73.56}, - {14.73, 10.45}, - {-31.23, 50.42}, - {6.18, 40.10}, - {17.09, 61.26}, - {18.50, 42.26}, - {19.17, 10.67}, - {51.10, 50.14}, - {-42.52, 76.67}, - {-5.54, 53.06}, - {33.70, 56.65}, - {-0.44, 6.76}, - {-7.42, 6.89}, - {19.24, 9.46}, - {48.41, 43.99}, - {3.87, 12.42}, - {-16.32, 11.94}, - {8.37, 45.34}, - {-20.69, 87.66}, - {19.71, 56.72}, - {-48.50, 33.76}, - {-0.57, 7.13}, - {-22.71, 11.26}, - {-27.73, 68.86}, - {-11.59, 33.48}, - {-9.62, 7.36}, - {15.89, 44.50}, - {-32.81, 30.96}, - {-18.53, 58.34}, - {-9.41, 55.15}, - {11.33, 59.36}, - {-7.88, 9.24}, - {13.91, 43.66}, - {-38.15, 64.22}, - {4.54, 3.59}, - {8.44, 35.80}, - {-1.29, 25.84}, - {26.64, 8.86}, - {19.44, 23.93}, - {8.31, 39.70}, - {21.07, 49.26}, - {-24.77, 69.02}, - {-34.89, 49.32}, - {-23.70, 64.79}, - {-7.06, 5.59}, - {4.13, 67.73}, - {13.44, 30.78}, - {36.07, 63.89}, - {-53.67, 23.06}, - {5.35, 33.70}, - {23.17, 45.78}, - {-0.85, 2.44}, - {15.12, 6.04}, - {23.63, 71.56}, - {20.37, 31.88}, - {17.50, 51.67}, - {-25.60, 17.35}, - {56.86, 67.97}, - {28.63, 81.59}, - {25.38, 56.49}, - {0.05, 18.79}, - {-13.60, 30.47}, - {4.80, 8.17}, - {4.55, 23.00}, - {33.94, 19.94}, - {4.04, 57.01}, - {43.61, 50.83}, - {-5.06, 10.59}, - {-16.60, 43.62}, - {-14.17, 14.19}, - {-1.97, 59.94}, - {-1.25, 26.76}, - {-22.66, 69.63}, - {0.03, 0.23}, - {-26.76, 54.82}, - {-23.82, 41.05}, - {-49.83, 52.38}, - {-24.58, 21.18}, - {20.76, 61.75}, - {-12.48, 26.36}, - {-37.73, 52.56}, - {6.00, 68.90}, - {9.32, 27.67}, - {0.36, 10.88}, - {-2.45, 5.87}, - {36.49, 74.56}, - {38.31, 57.71}, - {-35.46, 78.25}, - {1.62, 7.20}, - {8.75, 40.70}, - {-22.91, 58.17}, - {25.14, 55.26}, - {-7.33, 17.05}, - {-0.86, 95.47}, - {-27.65, 56.11}, - {-2.21, 12.53}, - {-54.69, 81.45}, - {9.02, 24.97}, - {-39.56, 35.42}, - {3.90, 17.48}, - {-4.84, 9.43}, - {7.63, 3.67}, - {-1.49, 9.99}, - {6.07, 96.66}, - {11.55, 69.81}, - {0.06, 4.54}, - {29.61, 22.63}, - {-0.18, 58.41}, - {4.87, 32.02}, - {-8.74, 5.88}, - {-6.42, 42.08}, - {-19.85, 77.38}, - {-29.51, 18.18}, - {47.64, 39.05}, - {-49.21, 69.14}, - {16.27, 29.14}, - {47.13, 57.96}, - {-5.88, 17.20}, - {7.39, 17.73}, - {-2.63, 76.94}, - {-8.43, 67.80}, - {17.66, 95.65}, - {-3.78, 105.43}, - {-19.35, 19.33}, - {-22.13, 85.25}, - {-32.01, 51.45}, - {33.34, 27.27}, - {4.76, 45.63}, - {20.07, 38.73}, - {16.43, 26.11}, - {12.41, 35.49}, - {-9.54, 69.75}, - {-15.05, 44.52}, - {-35.58, 48.02}, - {-26.35, 43.57}, - {17.04, 18.66}, - {25.06, 28.94}, - {-20.65, 8.61}, - {31.60, 24.50}, - {-39.23, 39.05}, - {8.47, 75.50}, - {-13.14, 71.52}, - {3.44, 4.81}, - {11.79, 114.92}, - {16.71, 37.99}, - {-11.03, 32.07}, - {48.07, 85.39}, - {10.42, 8.37}, - {0.67, 17.83}, - {-7.51, 24.17}, - {-6.98, 14.83}, - {8.26, 18.75}, - {6.14, 42.31}, - {-13.44, 58.32}, - {20.77, 41.19}, - {-5.08, 24.90}, - {0.02, 44.55}, - {40.65, 56.02}, - {-49.38, 47.95}, - {-1.62, 47.74}, - {65.36, 60.27}, - {10.12, 69.99}, - {-12.80, 62.38}, - {-19.28, 66.58}, - {12.35, 51.40}, - {-16.15, 41.69}, - {8.46, 64.81}, - {-37.44, 42.07}, - {-6.31, 17.43}, - {-28.52, 42.42}, - {-36.85, 35.12}, - {39.58, 17.97}, - {-12.11, 6.90}, - {49.39, 22.67}, - {49.25, 59.28}, - {-13.11, 15.93}, - {-36.76, 29.92}, - {9.02, 8.57}, - {-3.52, 108.92}, - {26.81, 33.21}, - {-25.78, 35.35}, - {23.31, 19.43}, - {30.72, 38.03}, - {8.59, 14.15}, - {3.84, 62.92}, - {-0.07, 16.04}, - {16.99, 40.18}, - {1.44, 58.64}, - {-52.31, 15.21}, - {26.47, 12.18}, - {29.26, 49.76}, - {32.75, 37.25}, - {28.24, 16.85}, - {-2.05, 3.25}, - {-33.27, 56.51}, - {5.90, 30.11}, - {-16.63, 93.02}, - {14.99, 47.54}, - {51.31, 27.46}, - {13.69, 76.22}, - {-42.35, 32.55}, - {37.88, 82.98}, - {-2.92, 27.40}, - {-13.59, 12.14}, - {-13.48, 30.24}, - {-67.06, 11.26}, - {-0.87, 59.62}, - {4.24, 18.59}, - {17.98, 68.03}, - {14.82, 46.36}, - {11.00, 12.77}, - {29.22, 20.92}, - {3.95, 5.68}, - {-9.54, 31.57}, - {24.37, 57.06}, - {2.50, 9.51}, - {26.05, 58.50}, - {10.56, 48.73}, - {-5.65, 21.94}, - {36.16, 23.04}, - {2.42, 10.68}, - {6.56, 61.46}, - {-6.60, 41.32}, - {31.49, 40.93}, - {-18.71, 19.55}, - {43.97, 75.72}, - {9.14, 33.64}, - {19.30, 25.13}, - {-12.38, 38.43}, - {-24.39, 35.99}, - {-5.55, 25.66}, - {-11.71, 21.07}, - {17.12, 15.80}, - {-28.85, 23.36}, - {-21.31, 29.96}, - {-3.33, 6.83}, - {41.43, 36.06}, - {10.13, 52.06}, - {0.30, 8.45}, - {-39.11, 68.91}, - {-33.57, 89.22}, - {18.81, 17.35}, - {-6.22, 28.36}, - {-3.80, 82.00}, - {-1.35, 81.71}, - {9.18, 59.90}, - {-44.29, 28.03}, - {-16.17, 40.76}, - {-5.22, 9.32}, - {-2.14, 9.00}, - {44.18, 67.32}, - {-1.76, 21.32}, - {18.82, 94.67}, - {-23.49, 86.50}, - {-35.23, 74.91}, - {-12.32, 12.48}, - {7.18, 8.81}, - {-4.30, 5.64}, - {11.90, 36.04}, - {-39.71, 28.47}, - {-48.46, 18.94}, - {31.11, 75.20}, - {-10.67, 29.61}, - {-31.00, 35.43}, - {6.53, 44.56}, - {-0.88, 1.57}, - {-13.32, 38.14}, - {0.14, 29.57}, - {-23.39, 42.20}, - {5.95, 67.32}, - {17.38, 33.26}, - {-2.36, 60.71}, - {-48.30, 55.33}, - {-60.27, 69.27}, - {4.13, 92.76}, - {12.63, 12.06}, - {-45.40, 53.50}, - {9.11, 72.28}, - {45.68, 26.21}, - {-1.17, 39.19}, - {-21.89, 31.92}, - {-2.45, 59.04}, - {24.16, 70.02}, - {-16.86, 17.05}, - {59.15, 59.47}, - {36.45, 41.38}, - {-17.30, 68.80}, - {8.35, 66.77}, - {4.78, 20.56}, - {-1.41, 7.70}, - {-0.27, 29.10}, - {-18.33, 69.13}, - {10.10, 22.61}, - {8.17, 28.85}, - {-10.28, 82.05}, - {27.25, 48.21}, - {-29.61, 49.95}, - {4.42, 48.59}, - {24.46, 81.28}, - {-9.60, 10.00}, - {-37.27, 26.90}, - {14.15, 78.71}, - {-5.04, 81.46}, - {-55.91, 68.15}, - {11.48, 61.76}, - {0.33, 18.74}, - {-1.75, 29.29}, - {-28.27, 23.57}, - {2.14, 32.10}, - {-0.58, 14.09}, - {-10.48, 73.71}, - {30.11, 22.64}, - {-30.62, 61.05}, - {7.14, 52.31}, - {-31.75, 8.68}, - {-25.60, 6.33}, - {10.81, 57.00}, - {1.58, 2.68}, - {-4.03, 4.49}, - {-69.40, 26.65}, - {34.97, 57.23}, - {-41.39, 85.26}, - {-56.66, 50.02}, - {26.67, 58.89}, - {36.97, 69.48}, - {17.62, 53.74}, - {-18.06, 67.20}, - {54.54, 42.92}, - {14.62, 28.66}, - {-17.46, 40.70}, - {37.49, 30.72}, - {-27.58, 81.20}, - {28.17, 29.78}, - {34.89, 64.55}, - {-14.73, 36.98}, - {-0.38, 14.23}, - {-22.73, 20.62}, - {3.66, 30.99}, - {4.21, 1.91}, - {-17.97, 61.45}, - {13.89, 44.10}, - {-9.36, 11.27}, - {-19.45, 71.53}, - {-30.31, 16.20}, - {21.83, 98.07}, - {51.73, 58.32}, - {15.61, 25.75}, - {-8.92, 16.21}, - {5.57, 7.03}, - {-31.94, 42.30}, - {-41.53, 54.41}, - {-34.46, 6.55}, - {48.82, 39.18}, - {-7.99, 45.35}, - {-58.46, 49.26}, - {6.76, 13.13}, - {7.31, 45.21}, - {-20.81, 46.15}, - {18.17, 19.43}, - {-11.37, 30.95}, - {-22.46, 82.83}, - {-8.81, 10.85}, - {-22.15, 37.62}, - {28.11, 13.51}, - {1.90, 19.58}, - {-33.67, 62.66}, - {-5.18, 36.44}, - {-14.59, 26.19}, - {-11.07, 5.77}, - {-10.54, 23.97}, - {11.13, 81.69}, - {37.26, 98.19}, - {-0.45, 58.06}, - {32.69, 21.79}, - {-1.75, 41.90}, - {-9.42, 33.26}, - {3.90, 3.16}, - {22.57, 17.60}, - {29.61, 93.77}, - {0.47, 16.32}, - {0.35, 2.00}, - {-24.37, 73.72}, - {40.52, 71.85}, - {3.95, 28.92}, - {18.43, 68.77}, - {20.38, 32.06}, - {36.49, 34.30}, - {32.78, 26.76}, - {-12.45, 23.75}, - {-17.04, 40.20}, - {-67.58, 42.30}, - {44.14, 40.41}, - {-20.29, 54.82}, - {-25.76, 25.64}, - {15.24, 59.03}, - {-24.18, 40.82}, - {20.78, 49.10}, - {-36.53, 21.06}, - {35.15, 44.67}, - {23.56, 47.18}, - {26.83, 31.04}, - {-6.04, 40.57}, - {17.77, 42.20}, - {29.56, 14.24}, - {-14.93, 7.49}, - {42.65, 43.61}, - {4.09, 60.41}, - {17.54, 29.38}, - {-40.77, 79.19}, - {-20.66, 41.15}, - {-16.10, 16.23}, - {-36.23, 71.30}, - {-5.32, 60.14}, - {14.84, 49.12}, - {13.98, 25.01}, - {-15.22, 67.15}, - {40.35, 61.61}, - {30.94, 35.53}, - {17.11, 72.57}, - {23.87, 30.84}, - {-31.95, 79.27}, - {6.63, 52.97}, - {-12.48, 9.24}, - {-41.66, 50.25}, - {-23.34, 27.06}, - {9.40, 35.27}, - {1.66, 10.57}, - {30.45, 79.29}, - {29.85, 59.03}, - {4.19, 41.60} -}; - diff --git a/benchmarks/vec-cmplxmult/dataset_test.h b/benchmarks/vec-cmplxmult/dataset_test.h deleted file mode 100644 index 1f2fed7..0000000 --- a/benchmarks/vec-cmplxmult/dataset_test.h +++ /dev/null @@ -1,29 +0,0 @@ -// See LICENSE for license details. - - -#define DATA_SIZE 4 - -struct Complex input1_data[DATA_SIZE] = -{ - {0.37, 4.09}, - {5.09, 0.02}, - {6.75, 3.30}, - {1.19, 0.58} -}; - -struct Complex input2_data[DATA_SIZE] = -{ - {7.51, 3.02}, - {1.69, 8.91}, - {3.16, 5.16}, - {8.56, 1.38} -}; - -struct Complex verify_data[DATA_SIZE] = -{ - {-9.55, 31.87}, - {8.45, 45.39}, - {4.34, 45.27}, - {9.41, 6.59} -}; - diff --git a/benchmarks/vec-cmplxmult/vec_cmplxmult_asm.S b/benchmarks/vec-cmplxmult/vec_cmplxmult_asm.S deleted file mode 100644 index dff057e..0000000 --- a/benchmarks/vec-cmplxmult/vec_cmplxmult_asm.S +++ /dev/null @@ -1,148 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# cmplxmult function (assembly version) -#----------------------------------------------------------------------------- - - -#-------------------------------------------------------------------------- -# Headers and Defines -#-------------------------------------------------------------------------- - -# Here are some defines that make writing assembly code easier. - -# I'm using the knowledge that rN will be placed in register a0, rA will be -# placed into register a1, etc., based on the calling convention for functions. - - -#define rN a0 -#define rA a1 -#define rB a2 -#define rC a3 - -#define rVlen a6 -#define rStride a7 - -#define rAI t0 -#define rBI t1 -#define rCI t2 - -# WARNING: do not write to the s0,...,s9 registers without first saving them to -# the stack. - -#-------------------------------------------------------------------------- -# void scalar_cmplxmult_asm( int n, float a[], float b[], float c[] ) -#-------------------------------------------------------------------------- - - .text - .align 2 - .globl scalar_cmplxmult_asm - .type scalar_cmplxmult_asm,@function - -scalar_cmplxmult_asm: - - # ***** Scalar Example ***** - - blez rN, done # exit early if n < 0 - -loop: - # The following code is a naive implementation... - # Re-ordering instructions may increase performance, also, - # RISC-V supports instrucitons such as the "fmuladd" and "fmulsub". - # fmsub.s fa2,fa4,fa3,ft1 - # Finally, unrolling and other fun transformations can also provide - # performance gains. - - flw f2, 0(rA) - flw f3, 4(rA) - flw f4, 0(rB) - flw f5, 4(rB) - fmul.s f6, f2, f4 - fmul.s f7, f3, f5 - fmul.s f8, f3, f4 - fmul.s f9, f2, f5 - fsub.s f10, f6, f7 - fadd.s f11, f8, f9 - fsw f10, 0(rC) - fsw f11, 4(rC) - addi rN, rN, -1 - addi rA, rA, 8 - addi rB, rB, 8 - addi rC, rC, 8 - bne rN, zero, loop -done: - ret - - -#-------------------------------------------------------------------------- -# void vt_cmplxmult_asm( int n, float a[], float b[], float c[] ) -#-------------------------------------------------------------------------- - - - # ***** Vector-Thread Example ***** - - .globl vt_cmplxmult_asm - .type vt_cmplxmult_asm,@function - - # HINT: because you are dealing with an array of structures, a regular, - # vanilla vector-load/vector-store won't work here! - -vt_cmplxmult_asm: - - blez rN, cpdone - la a4, vtcode - li rStride, 8 - - vvcfgivl rVlen, rN, 1, 7 - -stripmineloop: - - # ADD YOUR CODE HERE.... - vsetvl rVlen, rN # set the vector length - # rN is the desired (application) vector length - # rVLen is what vector length we were given - - vflstw vf2, rA, rStride # real number vector load of A - addi rAI, rA, 4 - vflstw vf4, rB, rStride # real number vector load of B - addi rBI, rB, 4 - vflstw vf3, rAI, rStride #imaginary number vector load of A - vflstw vf5, rBI, rStride #imaginary vector number load of B - - vf 0(a4) # jump to vector-fetch code - - vfsstw vf0, rC, rStride # real number vector store C - addi rCI, rC, 4 - vfsstw vf1, rCI, rStride # imaginary - - slli a5, rVlen, 3 - sub rN, rN, rVlen # book keeping - add rA, rA, a5 - add rB, rB, a5 - add rC, rC, a5 - bne rN, zero, stripmineloop - # Step 0: set the vector length - # Step 1: perform your vector loads - # Step 2: jump to the vector-fetch code to perform the calculation - # Step 3: perform the vector store - # Step 4: book keeping, update the pointers, etc. - -cpdone: - fence.v.l - ret - -vtcode: - # ADD YOUR VECTOR-ELEMENT CODE HERE ... - fmul.s f0, f2, f4 - fmsub.s f0, f3, f5, f0 - - fmul.s f1, f2, f5 - fmadd.s f1, f3, f4, f1 - stop - - # The C code uses a jalr instruction to call this function - # so we can use a jr to return back to where the function - # was called. Also known as "ret", for "return". - - ret - diff --git a/benchmarks/vec-cmplxmult/vec_cmplxmult_main.c b/benchmarks/vec-cmplxmult/vec_cmplxmult_main.c deleted file mode 100644 index 62521c4..0000000 --- a/benchmarks/vec-cmplxmult/vec_cmplxmult_main.c +++ /dev/null @@ -1,319 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// Vector-Thread Complex Multiply benchmark -//-------------------------------------------------------------------------- -// -// This benchmark multiplies two complex numbers together. The input data (and -// reference data) should be generated using the cmplxmult_gendata.pl perl -// script and dumped to a file named dataset.h. The riscv-gcc toolchain does -// not support system calls so printf's can only be used on a host system, not -// on the riscv-v processor simulator itself. -// -// HOWEVER: printstr() and printhex() are provided, for a primitive form of -// printing strings and hexadecimal values to stdout. - - -// Choose which implementation you wish to test... but leave only one on! -// (only the first one will be executed). -//#define SCALAR_C -//#define SCALAR_ASM -#define VT_ASM - -//-------------------------------------------------------------------------- -// Macros - -// Set HOST_DEBUG to 1 if you are going to compile this for a host -// machine (ie Athena/Linux) for debug purposes and set HOST_DEBUG -// to 0 if you are compiling with the smips-gcc toolchain. - -#ifndef HOST_DEBUG -#define HOST_DEBUG 0 -#endif - -// Set PREALLOCATE to 1 if you want to preallocate the benchmark -// function before starting stats. If you have instruction/data -// caches and you don't want to count the overhead of misses, then -// you will need to use preallocation. - -#ifndef PREALLOCATE -#define PREALLOCATE 0 -#endif - -// Set SET_STATS to 1 if you want to carve out the piece that actually -// does the computation. - -#ifndef SET_STATS -#define SET_STATS 0 -#endif - -//-------------------------------------------------------------------------- -// Host Platform Includes - -#if HOST_DEBUG - #include - #include -#else -void printstr(const char*); -#endif - -#include "util.h" - - -//-------------------------------------------------------------------------- -// Complex Value Structs - -struct Complex -{ - float real; - float imag; -}; - - -//-------------------------------------------------------------------------- -// Input/Reference Data - -//#include "dataset_test.h" -#include "dataset.h" - - -//-------------------------------------------------------------------------- -// Helper functions - -float absolute( float in) -{ - if (in > 0) - return in; - else - return -in; -} - - -// are two floating point numbers "close enough"? -// this is pretty loose, because Perl is giving me pretty terrible answers -int close_enough(float a, float b) -{ - int close_enough = 1; - - if ( absolute(a) > 1.10*absolute(b) - || absolute(a) < 0.90*absolute(b) - || absolute(a) > 1.10*absolute(b) - || absolute(a) < 0.90*absolute(b)) - { - if (absolute(absolute(a) - absolute(b)) > 0.1) - { - close_enough = 0; - } - } - - return close_enough; -} - -int verify( int n, struct Complex test[], struct Complex correct[] ) -{ - int i; - for ( i = 0; i < n; i++ ) { - if ( !close_enough(test[i].real, correct[i].real) - || !close_enough(test[i].imag, correct[i].imag)) - { -#if HOST_DEBUG - printf(" test[%d] : {%3.2f, %3.2f}\n", i, test[i].real, test[i].imag); - printf(" corr[%d] : {%3.2f, %3.2f}\n", i, correct[i].real, correct[i].imag); -#endif - // tell us which index fails + 10 - // (so that if i==0,i==1 fails, we don't - // think it was a 'not-finished yet' or pass) -// return i+10; - return 2; - } - } - return 1; -} - -//#if HOST_DEBUG -void printComplexArray( char name[], int n, struct Complex arr[] ) -{ -#if HOST_DEBUG - int i; - printf( " %10s :", name ); - for ( i = 0; i < n; i++ ) - printf( " {%03.2f,%03.2f} ", arr[i].real, arr[i].imag ); - printf( "\n" ); -#else - int i; - printstr( name ); - for ( i = 0; i < n; i++ ) - { - printstr(" {"); - printhex((int) arr[i].real); - printstr(","); - printhex((int) arr[i].imag); - printstr("}"); - } - printstr( "\n" ); -#endif -} -//#endif - - - -void finishTest( int correct, long long num_cycles, long long num_retired ) -{ - int toHostValue = correct; -#if HOST_DEBUG - if ( toHostValue == 1 ) - printf( "*** PASSED ***\n" ); - else - printf( "*** FAILED *** (tohost = %d)\n", toHostValue ); - exit(0); -#else - // we no longer run in -testrun mode, which means we can't use - // the tohost register to communicate "test is done" and "test results" - // so instead we will communicate through print* functions! - if ( correct == 1 ) - { - printstr( "*** PASSED *** (num_cycles = 0x" ); - printhex(num_cycles); - printstr( ", num_inst_retired = 0x"); - printhex(num_retired); - printstr( ")\n" ); - } - else - { - printstr( "*** FAILED *** (num_cycles = 0x"); - printhex(num_cycles); - printstr( ", num_inst_retired = 0x"); - printhex(num_retired); - printstr( ")\n" ); - } - exit(); -#endif -} - - - - -// deprecated - cr10/stats-enable register no longer exists -void setStats( int enable ) -{ -#if ( !HOST_DEBUG && SET_STATS ) - asm( "mtpcr %0, cr10" : : "r" (enable) ); -#endif -} - -long long getCycles() -{ - long long cycles = 1337; -#if ( !HOST_DEBUG && SET_STATS ) - __asm__ __volatile__( "rdcycle %0" : "=r" (cycles) ); -#endif - return cycles; -} - -long long getInstRetired() -{ - long long inst_retired = 1338; -#if ( !HOST_DEBUG && SET_STATS ) - __asm__ __volatile__( "rdinstret %0" : "=r" (inst_retired) ); -#endif - return inst_retired; -} - -//-------------------------------------------------------------------------- -// complex multiply function - -// scalar C implementation -void cmplxmult( int n, struct Complex a[], struct Complex b[], struct Complex c[] ) -{ - int i; - for ( i = 0; i < n; i++ ) - { - c[i].real = (a[i].real * b[i].real) - (a[i].imag * b[i].imag); - c[i].imag = (a[i].imag * b[i].real) + (a[i].real * b[i].imag); - } -} - -// assembly implementations can be found in *_asm.S - -//-------------------------------------------------------------------------- -// Main - -int main( int argc, char* argv[] ) -{ - struct Complex results_data[DATA_SIZE]; - long long start_cycles = 0; - long long stop_cycles = 0; - long long num_cycles; - long long start_retired = 0; - long long stop_retired = 0; - long long num_retired; - - // Output the input array - -#if HOST_DEBUG - printComplexArray( "input1", DATA_SIZE, input1_data ); - printComplexArray( "input2", DATA_SIZE, input2_data ); - printComplexArray( "verify", DATA_SIZE, verify_data ); -#endif - - // -------------------------------------------------- - // If needed we preallocate everything in the caches - -#if PREALLOCATE - -#ifdef SCALAR_C - cmplxmult( DATA_SIZE, input1_data, input2_data, results_data ); -#else -#ifdef SCALAR_ASM - scalar_cmplxmult_asm( DATA_SIZE, input1_data, input2_data, results_data ); -#else -#ifdef VT_ASM - vt_cmplxmult_asm( DATA_SIZE, input1_data, input2_data, results_data ); -#endif -#endif -#endif - -#endif - - // -------------------------------------------------- - // Do the cmplxmult - - start_cycles = getCycles(); - start_retired = getInstRetired(); - -#ifdef SCALAR_C - cmplxmult( DATA_SIZE, input1_data, input2_data, results_data ); -#else -#ifdef SCALAR_ASM - #if HOST_DEBUG==0 - scalar_cmplxmult_asm( DATA_SIZE, input1_data, input2_data, results_data ); - #endif -#else -#ifdef VT_ASM - #if HOST_DEBUG==0 - vt_cmplxmult_asm( DATA_SIZE, input1_data, input2_data, results_data ); - #endif -#endif -#endif -#endif - - stop_cycles = getCycles(); - stop_retired = getInstRetired(); - num_cycles = stop_cycles - start_cycles; - num_retired = stop_retired - start_retired; - - // -------------------------------------------------- - // Print out the results - -#if HOST_DEBUG - printComplexArray( "results", DATA_SIZE, results_data ); - printComplexArray( "verify ", DATA_SIZE, verify_data ); -#endif - - - // -------------------------------------------------- - // Check the results - int correct = verify( DATA_SIZE, results_data, verify_data ); - finishTest(correct, num_cycles, num_retired); - -} diff --git a/benchmarks/vec-fft/bmark.mk b/benchmarks/vec-fft/bmark.mk deleted file mode 100644 index 46a2835..0000000 --- a/benchmarks/vec-fft/bmark.mk +++ /dev/null @@ -1,41 +0,0 @@ -#======================================================================= -# UCB CS250 Makefile fragment for benchmarks -#----------------------------------------------------------------------- -# -# Each benchmark directory should have its own fragment which -# essentially lists what the source files are and how to link them -# into an riscv and/or host executable. All variables should include -# the benchmark name as a prefix so that they are unique. -# - -vec-fft_data_src = fft-data.c - -vec-fft_c_src = \ - vec-fft_main.c \ - vec-fft.c \ - $(vec-fft_data_src) - -vec-fft_riscv_src = \ - crt.S \ - vec-vfft.S - -vec-fft_c_objs = $(patsubst %.c, %.o, $(vec-fft_c_src)) -vec-fft_riscv_objs = $(patsubst %.S, %.o, $(vec-fft_riscv_src)) - -vec-fft_data_bin = fft-data-gen -$(vec-fft_data_src): $(vec-fft_data_bin) - ./$< $(FFT_FLOATING_PREC) $(FFT_SIZE) > $@ - -vec-fft_host_bin = vec-fft.host -$(vec-fft_host_bin): $(vec-fft_c_src) -# $(HOST_COMP) $^ -o $(vec-fft_host_bin) - -RISCV_LINK_SYSCALL = $(bmarkdir)/common/syscalls.c -lc - -vec-fft_riscv_bin = vec-fft.riscv -$(vec-fft_riscv_bin): $(vec-fft_c_objs) $(vec-fft_riscv_objs) - $(RISCV_LINK) $(RISCV_LINK_SYSCALL) $(vec-fft_c_objs) $(vec-fft_riscv_objs) -o $(vec-fft_riscv_bin) - -junk += \ - $(vec-fft_data_src) $(vec-fft_c_objs) $(vec-fft_riscv_objs) \ - $(vec-fft_host_bin) $(vec-fft_riscv_bin) diff --git a/benchmarks/vec-fft/cvt16.c b/benchmarks/vec-fft/cvt16.c deleted file mode 100644 index ef769b0..0000000 --- a/benchmarks/vec-fft/cvt16.c +++ /dev/null @@ -1,122 +0,0 @@ -// See LICENSE for license details. - -#include "cvt16.h" - -#define H_BIAS (UINT16_C(0xf)) -#define H_F_MASK (UINT16_C(0x03FF)) -#define H_E_MASK (UINT16_C(0x7C00)) -#define H_E_SHIFT (10) -#define H_S_MASK (UINT16_C(0x8000)) - -#define H_QNAN (H_F_MASK) - -#define S_BIAS (UINT32_C(0x7F)) -#define S_F_MASK (UINT32_C(0x007fffff)) -#define S_E_MASK (UINT32_C(0x7f800000)) -#define S_E_SHIFT (23) -#define S_S_MASK (UINT32_C(0x80000000)) - -#define S_QNAN (S_F_MASK) - -#define PAD (S_E_SHIFT - H_E_SHIFT) - -uint_fast32_t cvt_hs(uint_fast16_t x) -{ -#define MSB (UINT32_C(0x00800000)) - uint_fast32_t frac, exp, sign; - frac = (x & H_F_MASK) << PAD; - exp = (x & H_E_MASK); - sign = (x & H_S_MASK); - - switch (exp) { - case 0: - if (frac) { /* Denormal */ - exp = S_BIAS - 14; - /* Adjust fraction for implicit leading 1-bit */ - for (; !(frac & MSB); frac <<= 1, exp--); - frac &= ~(MSB); - exp <<= S_E_SHIFT; - } - break; - - case H_E_MASK: /* Infinity and NaN */ - exp = S_E_MASK; - if (frac) { /* Set padding bits for NaN */ - frac |= (1 << PAD) - 1; - } - break; - default: - exp += (S_BIAS - H_BIAS) << H_E_SHIFT; /* Re-bias */ - exp <<= PAD; - } - return (sign << 16) | exp | frac; -#undef MSB -} - -/* - * LSB : frac[13] - * Guard bit (G): frac[12] - * Round bit (R): frac[11] - * Sticky bit (S): OR of frac[10..0] - * - * RTZ: - * truncate - * RUP: - * 000 : exact - * else : round up - * RDN: - * 000 : exact - * else : round down - * RNE: - * 0xx : round down - * 100 : tie; round up if LSB is 1 - * 101 : round up - * 110 : round up - * 111 : round up - */ -uint_fast16_t cvt_sh(uint_fast32_t x, int rm) -{ -#define MSB UINT16_C(0x0400) - uint_fast32_t frac, exp, sign; - int e; - sign = (x & S_S_MASK) >> 16; - exp = (x & S_E_MASK); - if (exp && exp != S_E_MASK) { - int inc; - inc = 0; - switch (rm) { - case RNE: - /* Round up if G is set and either R, S, - or the bit before G is non-zero */ - inc = (x & 0x1000) && (x & 0x2fff); - break; - case RUP: - inc = ((x & 0x1fff) != 0) && (!sign); - break; - case RDN: - inc = ((x & 0x1fff) != 0) && sign; - break; - } - x += inc << PAD; - exp = (x & S_E_MASK); - } - frac = (x & S_F_MASK) >> PAD; - - e = (exp >> S_E_SHIFT) - S_BIAS; - if (e < -24) { /* Round to zero */ - return sign; - } else if (e < -14) { /* Denormal */ - frac = (frac | MSB) >> (-e - 14); - return sign | frac; - } else if (e < 16) { - exp = (e + H_BIAS) << H_E_SHIFT; - } else if (e < 127) { /* Round to infinity */ - exp = H_E_MASK; - frac = 0; - } else { - /* Infinity and NaN */ - } - return sign | exp | frac; -#undef MSB -} - diff --git a/benchmarks/vec-fft/cvt16.h b/benchmarks/vec-fft/cvt16.h deleted file mode 100644 index 3d45f01..0000000 --- a/benchmarks/vec-fft/cvt16.h +++ /dev/null @@ -1,19 +0,0 @@ -// See LICENSE for license details. - -#ifndef _CVT16_H -#define _CVT16_H - -#include - -extern uint_fast32_t cvt_hs(uint_fast16_t); -extern uint_fast16_t cvt_sh(uint_fast32_t, int); - -enum riscv_rm { - RNE = 0, /* Round to nearest; ties to even */ - RTZ = 1, /* Round towards zero (truncate) */ - RDN = 2, /* Round towards negative infinity (down) */ - RUP = 3, /* Round towards positive infinity (up) */ - RMM = 4, /* Round to nearest; ties to max magnitude */ -}; - -#endif diff --git a/benchmarks/vec-fft/cvt_fft.c b/benchmarks/vec-fft/cvt_fft.c deleted file mode 100644 index 94884b0..0000000 --- a/benchmarks/vec-fft/cvt_fft.c +++ /dev/null @@ -1,39 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include - -#include "cvt16.h" - -typedef float fftval_t; -#include "fft_data_generic.c" - -static void _array(const char *s, const fftval_t *v, unsigned int n) -{ - union single { - float f; - uint32_t u; - } bits; - unsigned int i; - - printf("fftval_t %s[%u] = { ", s, n); - for (i = 0; i < n; i++) { - bits.f = v[i]; - printf("0x%04" PRIx16 ", ", cvt_sh(bits.u, RNE)); - } - puts("};"); -} - -#define array(v) _array(#v, (v), (sizeof(v) / sizeof(0[v]))) - -int main(void) -{ - array(input_data_real); - array(input_data_imag); - array(output_data_real); - array(output_data_imag); - array(tf_real); - array(tf_imag); - return 0; -} diff --git a/benchmarks/vec-fft/data.c b/benchmarks/vec-fft/data.c deleted file mode 100644 index bf8a18c..0000000 --- a/benchmarks/vec-fft/data.c +++ /dev/null @@ -1,23 +0,0 @@ -// See LICENSE for license details. - -#include "fft_const.h" - -#if !defined(FP_HALF) - -fftval_t input_data_real[ 128 ] = { 0.639426798458, 0.0250107552227, 0.275029318369, 0.223210738149, 0.736471214164, 0.676699487423, 0.892179567705, 0.0869388326294, 0.421921819685, 0.0297972194381, 0.218637974804, 0.505355288103, 0.0265359696839, 0.198837650687, 0.64988443778, 0.544941480603, 0.220440622041, 0.589265683876, 0.809430456678, 0.00649875967806, 0.805819251833, 0.698139394988, 0.340250516518, 0.155479499812, 0.957213072207, 0.336594545113, 0.0927458433801, 0.0967163768335, 0.847494366347, 0.603726031367, 0.807128273274, 0.729731786694, 0.536228091455, 0.973115763979, 0.378534377208, 0.552040631273, 0.829404664253, 0.618519752364, 0.861706900311, 0.577352145257, 0.704571836215, 0.0458243836557, 0.227898275652, 0.289387963602, 0.0797919769236, 0.232790886361, 0.10100142941, 0.27797360311, 0.635684444264, 0.36483217897, 0.370180967117, 0.209507030771, 0.266977822049, 0.936654587712, 0.648035385247, 0.609131005667, 0.171138648198, 0.72912679795, 0.163402493762, 0.379455441758, 0.989523350637, 0.639999759854, 0.556949743775, 0.68461425099, 0.84285192019, 0.775999911546, 0.229048071964, 0.032100243904, 0.315453048059, 0.267740875976, 0.210982843586, 0.942909714335, 0.876367626473, 0.314677880798, 0.655438665295, 0.395631901061, 0.914547589741, 0.458851852587, 0.264880166498, 0.246627507694, 0.561368134163, 0.262741608523, 0.584585990224, 0.897822883602, 0.39940050514, 0.219320759157, 0.997537606495, 0.509526293676, 0.0909094121738, 0.0471163754247, 0.109649130351, 0.627446041703, 0.792079364363, 0.4221599668, 0.063527706152, 0.381619286507, 0.99612138024, 0.529114345099, 0.971078377614, 0.860779702234, 0.0114810219428, 0.72072181936, 0.681710369027, 0.536970330409, 0.266825189953, 0.64096179858, 0.111552173596, 0.434765250669, 0.453723706329, 0.953815927521, 0.875852940378, 0.263389050751, 0.50058611305, 0.17865188053, 0.912627839345, 0.870518569837, 0.298444791449, 0.638949494866, 0.608970211438, 0.15283926855, 0.762510800075, 0.53937903012, 0.778626478631, 0.530353672195, 0.000571896127944, 0.324156057005, 0.0194767423858, 0.929098616265 }; -fftval_t input_data_imag[ 128 ] = { 0.878721877823, 0.831665529361, 0.307514125403, 0.0579251664942, 0.878009599204, 0.946949445298, 0.0856534520679, 0.485990463317, 0.0692125184684, 0.760602165257, 0.765834429307, 0.1283914645, 0.475282378099, 0.549803593495, 0.26505662894, 0.872433041085, 0.423137940201, 0.211798205442, 0.539296088779, 0.72993106909, 0.20115106339, 0.311716291301, 0.995149356661, 0.649878057639, 0.438100083915, 0.517575841036, 0.121004195868, 0.224697337032, 0.338085562147, 0.588308718457, 0.230114732597, 0.220217384452, 0.070993086009, 0.63110295727, 0.228941783811, 0.905420013006, 0.859635400254, 0.0708573498887, 0.238004634369, 0.668977778296, 0.21423680737, 0.132311848725, 0.935514240581, 0.571043093325, 0.472671026312, 0.784619424291, 0.807496997767, 0.190409914362, 0.0969308142288, 0.431051182406, 0.42357862302, 0.467024668037, 0.72907584946, 0.673364547293, 0.984165211366, 0.098417871152, 0.402621282102, 0.339302605395, 0.861672536353, 0.24865633392, 0.190208908441, 0.448613547833, 0.421881639834, 0.278545144667, 0.249806447882, 0.923265599276, 0.443130745053, 0.861349104762, 0.55032531245, 0.0505883295249, 0.999282468413, 0.83602758508, 0.968996257285, 0.926366983008, 0.848695734414, 0.166311110604, 0.485641125451, 0.213747299199, 0.401040292549, 0.0586353999722, 0.378973118977, 0.98530884378, 0.265203058172, 0.784070601949, 0.455008367339, 0.42300748599, 0.95731764086, 0.995422689493, 0.555768323406, 0.718408275296, 0.154796825274, 0.296707825495, 0.968709364969, 0.579180290816, 0.542195201374, 0.747975560379, 0.0571652729075, 0.584177594459, 0.50285038292, 0.852719892048, 0.157432727939, 0.960778903274, 0.0801114652406, 0.185824960981, 0.59503510645, 0.675212553604, 0.235203895001, 0.119886613947, 0.890287314129, 0.246215347789, 0.594519153533, 0.619381510332, 0.419224915336, 0.583672289291, 0.522782715532, 0.934706257736, 0.204259199424, 0.716191800789, 0.238685952616, 0.395785846791, 0.67169022296, 0.299997079799, 0.316177196272, 0.751864492414, 0.0725431144932, 0.458285522619, 0.998454440854, 0.996096447855 }; -fftval_t output_data_real[ 128 ] = { 61.954455353, -3.55833399529, -0.523354806008, -3.37768557289, 3.32687067509, -3.0237541092, -0.378319273514, 0.525689010981, 5.25658573479, -2.28074215555, -4.28723433346, -4.4277864945, 1.25302215885, -0.482791893995, -1.12845609406, -3.21089274844, -0.078505416643, -2.1193590094, 4.98495906311, -3.56979439628, 2.72333789593, 2.25668218204, 0.335271678442, -6.34334972936, 0.712532452309, 0.409291142904, -1.22780527711, 3.84865910019, 0.969858896916, 1.05979174012, -0.405273430345, 1.0161952607, 2.65666792497, -7.17797945232, 3.35748060331, -1.93036005449, 5.79228873407, 6.83679539719, 0.455509780838, -4.32751152407, -0.195720493898, -4.39713867575, 4.04962604613, 8.55532419691, 0.793886999177, 2.74675335418, 1.78534557879, -0.150461101563, 4.79269199365, -0.097190171132, -2.93509465459, 0.000498021981268, -3.87438881161, -5.12734321093, -2.12762472404, -1.16638837683, 3.59130812163, -0.816225274592, -0.806189352525, -1.15586605458, -1.92113200189, 0.855167926588, 0.603604208411, -0.409696855698, 2.88640009067, 2.56152175575, -1.09096481126, 0.828707821899, -0.962267817144, -0.81230709709, 1.16163049602, -0.695404120144, -4.20242999608, -2.92482265517, 1.02303060189, -2.70129415201, 0.525364381257, 2.49338291739, 2.34783772688, 4.95908644781, 0.177530769676, 5.16759926801, -2.55397551085, 1.48552350843, -4.50573276988, 0.451229866674, -6.81151821737, -5.00364260745, -0.98762260691, 5.226676945, 1.73684083074, -4.95366720132, 2.43429602647, 0.460297668808, 0.111897844813, -2.75691723482, 0.310022422864, -1.58528590021, -2.03689286823, -1.102027189, 3.51353594739, 1.0387748517, 3.84115211002, 3.81032001841, 2.43243605239, 0.621532229972, 5.36804043022, 7.69993469463, 3.63860246238, 3.633002238, -2.47462170952, 5.24293295589, 0.774064132507, -3.91244434865, 4.72655267242, -2.81469193189, 0.993153378271, -3.2354193083, 0.474071574908, 0.756162196284, -1.15709647317, 3.31705213122, -6.01086540873, 2.37742277745, 2.84408587391, -3.65152823413, -3.16692487284, 2.0388874191 }; -fftval_t output_data_imag[ 128 ] = { 64.7050383851, 0.698184545699, 3.42493175348, 5.66261938459, 1.00574698274, -3.1031255135, 5.20424207641, 2.0448135066, -4.63849287023, 2.51117736295, 1.41295259621, -2.45639979763, 5.86862949669, -4.29715899392, 1.97792740773, 1.61104358821, 3.55985554637, -0.852668449458, 3.78965920404, 1.11985520891, -3.08121666225, 4.31756301978, 7.89587646848, 5.66554418397, -6.1086556137, 5.62222049291, 4.34787054172, 0.668211990523, 2.31296531095, 5.41014021609, 0.453996830494, 2.7935768665, -2.34494675051, 1.17549556253, -2.36863533542, 3.34802654836, 0.810944712905, -3.46714468032, -4.00653978407, -3.0699493452, 5.34453801646, -1.15007047713, 1.48224491218, 1.96983218353, -2.35988258452, -3.83406990073, 1.05359927173, -2.62518260336, -2.26840395653, 4.53058951798, 4.37784201599, 1.74456564948, 1.17919710136, 5.85762105311, -2.17089571025, -0.186855334345, -2.78684050993, 11.2542088523, 3.53682020657, 0.921750647669, -2.75033375937, -2.39105725671, 5.69627942011, -2.14262056709, -3.24450591785, -4.88101239098, -0.82019947831, 1.73555667725, -2.67542169613, 2.70255959353, -1.56904900802, 0.813903077259, -4.79584930282, -0.827151380084, -0.153701429418, -2.79898616186, 2.31828350443, 2.21515556736, -3.40293773784, -0.162985084297, -3.05206321075, 1.75265985778, 1.95085395048, -4.00325708931, -4.0551434497, 1.05832733908, -0.462016761175, -10.7553551483, -1.34633968539, 3.33861851859, 0.17331130312, -3.50040264719, -0.469531530722, -6.75712678783, 0.101038910495, 4.60866018427, -1.43982416145, -0.388454731031, -2.90742197761, 0.187444758531, 2.66953361587, 6.87916789749, -1.25246099771, -0.80213619158, 0.490239247273, -4.52070544206, 1.9815151617, -4.46229763612, -2.28749790966, 0.771352499303, 2.42025535542, 2.63871825487, -3.99023733181, -0.379591050964, 2.64500129424, -1.50502365382, 1.35040224487, 6.8258533247, -2.71874835374, 5.97039779238, 3.11574368961, 6.0121394881, -1.19573643258, 2.25554012485, -0.82195704339, -1.2418186553, 1.11396326277, -1.87990085069 }; -fftval_t tf_real[ 128 ] = { 1.0, 0.998795456205, 0.995184726672, 0.989176509965, 0.980785280403, 0.970031253195, 0.956940335732, 0.941544065183, 0.923879532511, 0.903989293123, 0.881921264348, 0.85772861, 0.831469612303, 0.803207531481, 0.773010453363, 0.740951125355, 0.707106781187, 0.671558954847, 0.634393284164, 0.595699304492, 0.55557023302, 0.514102744193, 0.471396736826, 0.42755509343, 0.382683432365, 0.336889853392, 0.290284677254, 0.242980179903, 0.195090322016, 0.146730474455, 0.0980171403296, 0.0490676743274, 6.12323399574e-17, -0.0490676743274, -0.0980171403296, -0.146730474455, -0.195090322016, -0.242980179903, -0.290284677254, -0.336889853392, -0.382683432365, -0.42755509343, -0.471396736826, -0.514102744193, -0.55557023302, -0.595699304492, -0.634393284164, -0.671558954847, -0.707106781187, -0.740951125355, -0.773010453363, -0.803207531481, -0.831469612303, -0.85772861, -0.881921264348, -0.903989293123, -0.923879532511, -0.941544065183, -0.956940335732, -0.970031253195, -0.980785280403, -0.989176509965, -0.995184726672, -0.998795456205, -1.0, -0.998795456205, -0.995184726672, -0.989176509965, -0.980785280403, -0.970031253195, -0.956940335732, -0.941544065183, -0.923879532511, -0.903989293123, -0.881921264348, -0.85772861, -0.831469612303, -0.803207531481, -0.773010453363, -0.740951125355, -0.707106781187, -0.671558954847, -0.634393284164, -0.595699304492, -0.55557023302, -0.514102744193, -0.471396736826, -0.42755509343, -0.382683432365, -0.336889853392, -0.290284677254, -0.242980179903, -0.195090322016, -0.146730474455, -0.0980171403296, -0.0490676743274, -1.83697019872e-16, 0.0490676743274, 0.0980171403296, 0.146730474455, 0.195090322016, 0.242980179903, 0.290284677254, 0.336889853392, 0.382683432365, 0.42755509343, 0.471396736826, 0.514102744193, 0.55557023302, 0.595699304492, 0.634393284164, 0.671558954847, 0.707106781187, 0.740951125355, 0.773010453363, 0.803207531481, 0.831469612303, 0.85772861, 0.881921264348, 0.903989293123, 0.923879532511, 0.941544065183, 0.956940335732, 0.970031253195, 0.980785280403, 0.989176509965, 0.995184726672, 0.998795456205 }; -fftval_t tf_imag[ 128 ] = { -0.0, -0.0490676743274, -0.0980171403296, -0.146730474455, -0.195090322016, -0.242980179903, -0.290284677254, -0.336889853392, -0.382683432365, -0.42755509343, -0.471396736826, -0.514102744193, -0.55557023302, -0.595699304492, -0.634393284164, -0.671558954847, -0.707106781187, -0.740951125355, -0.773010453363, -0.803207531481, -0.831469612303, -0.85772861, -0.881921264348, -0.903989293123, -0.923879532511, -0.941544065183, -0.956940335732, -0.970031253195, -0.980785280403, -0.989176509965, -0.995184726672, -0.998795456205, -1.0, -0.998795456205, -0.995184726672, -0.989176509965, -0.980785280403, -0.970031253195, -0.956940335732, -0.941544065183, -0.923879532511, -0.903989293123, -0.881921264348, -0.85772861, -0.831469612303, -0.803207531481, -0.773010453363, -0.740951125355, -0.707106781187, -0.671558954847, -0.634393284164, -0.595699304492, -0.55557023302, -0.514102744193, -0.471396736826, -0.42755509343, -0.382683432365, -0.336889853392, -0.290284677254, -0.242980179903, -0.195090322016, -0.146730474455, -0.0980171403296, -0.0490676743274, -1.22464679915e-16, 0.0490676743274, 0.0980171403296, 0.146730474455, 0.195090322016, 0.242980179903, 0.290284677254, 0.336889853392, 0.382683432365, 0.42755509343, 0.471396736826, 0.514102744193, 0.55557023302, 0.595699304492, 0.634393284164, 0.671558954847, 0.707106781187, 0.740951125355, 0.773010453363, 0.803207531481, 0.831469612303, 0.85772861, 0.881921264348, 0.903989293123, 0.923879532511, 0.941544065183, 0.956940335732, 0.970031253195, 0.980785280403, 0.989176509965, 0.995184726672, 0.998795456205, 1.0, 0.998795456205, 0.995184726672, 0.989176509965, 0.980785280403, 0.970031253195, 0.956940335732, 0.941544065183, 0.923879532511, 0.903989293123, 0.881921264348, 0.85772861, 0.831469612303, 0.803207531481, 0.773010453363, 0.740951125355, 0.707106781187, 0.671558954847, 0.634393284164, 0.595699304492, 0.55557023302, 0.514102744193, 0.471396736826, 0.42755509343, 0.382683432365, 0.336889853392, 0.290284677254, 0.242980179903, 0.195090322016, 0.146730474455, 0.0980171403296, 0.0490676743274 }; - -#else - -fftval_t input_data_real[128] = { 0x391e, 0x2667, 0x3467, 0x3325, 0x39e4, 0x396a, 0x3b23, 0x2d90, 0x36c0, 0x27a1, 0x32ff, 0x380b, 0x26cb, 0x325d, 0x3933, 0x385c, 0x330e, 0x38b7, 0x3a7a, 0x1ea8, 0x3a72, 0x3996, 0x3572, 0x30fa, 0x3ba8, 0x3563, 0x2df0, 0x2e31, 0x3ac8, 0x38d4, 0x3a75, 0x39d6, 0x384a, 0x3bc9, 0x360e, 0x386b, 0x3aa3, 0x38f3, 0x3ae5, 0x389e, 0x39a3, 0x29de, 0x334b, 0x34a1, 0x2d1b, 0x3373, 0x2e77, 0x3473, 0x3916, 0x35d6, 0x35ec, 0x32b4, 0x3446, 0x3b7e, 0x392f, 0x38e0, 0x317a, 0x39d5, 0x313b, 0x3612, 0x3beb, 0x391f, 0x3875, 0x397a, 0x3abe, 0x3a35, 0x3354, 0x281c, 0x350c, 0x3449, 0x32c0, 0x3b8b, 0x3b03, 0x3509, 0x393e, 0x3655, 0x3b51, 0x3757, 0x343d, 0x33e4, 0x387e, 0x3434, 0x38ad, 0x3b2f, 0x3664, 0x3305, 0x3bfb, 0x3814, 0x2dd1, 0x2a08, 0x2f04, 0x3905, 0x3a56, 0x36c1, 0x2c11, 0x361b, 0x3bf8, 0x383c, 0x3bc5, 0x3ae3, 0x21e1, 0x39c4, 0x3974, 0x384c, 0x3445, 0x3921, 0x2f24, 0x36f5, 0x3742, 0x3ba1, 0x3b02, 0x3437, 0x3801, 0x31b8, 0x3b4d, 0x3af7, 0x34c6, 0x391d, 0x38df, 0x30e4, 0x3a1a, 0x3851, 0x3a3b, 0x383e, 0x10af, 0x3530, 0x24fc, 0x3b6f, }; -fftval_t input_data_imag[128] = { 0x3b08, 0x3aa7, 0x34ec, 0x2b6a, 0x3b06, 0x3b93, 0x2d7b, 0x37c7, 0x2c6e, 0x3a16, 0x3a20, 0x301c, 0x379b, 0x3866, 0x343e, 0x3afb, 0x36c5, 0x32c7, 0x3850, 0x39d7, 0x3270, 0x34fd, 0x3bf6, 0x3933, 0x3702, 0x3824, 0x2fbf, 0x3331, 0x3569, 0x38b5, 0x335d, 0x330c, 0x2c8b, 0x390c, 0x3353, 0x3b3e, 0x3ae1, 0x2c89, 0x339e, 0x395a, 0x32db, 0x303c, 0x3b7c, 0x3891, 0x3790, 0x3a47, 0x3a76, 0x3218, 0x2e34, 0x36e6, 0x36c7, 0x3779, 0x39d5, 0x3963, 0x3be0, 0x2e4c, 0x3671, 0x356e, 0x3ae5, 0x33f5, 0x3216, 0x372e, 0x36c0, 0x3475, 0x33fe, 0x3b63, 0x3717, 0x3ae4, 0x3867, 0x2a7a, 0x3bff, 0x3ab0, 0x3bc1, 0x3b69, 0x3aca, 0x3152, 0x37c5, 0x32d7, 0x366b, 0x2b81, 0x3610, 0x3be2, 0x343e, 0x3a46, 0x3748, 0x36c5, 0x3ba9, 0x3bf7, 0x3872, 0x39bf, 0x30f4, 0x34bf, 0x3bc0, 0x38a2, 0x3856, 0x39fc, 0x2b51, 0x38ac, 0x3806, 0x3ad2, 0x310a, 0x3bb0, 0x2d21, 0x31f2, 0x38c3, 0x3967, 0x3387, 0x2fac, 0x3b1f, 0x33e1, 0x38c2, 0x38f4, 0x36b5, 0x38ab, 0x382f, 0x3b7a, 0x3289, 0x39bb, 0x33a3, 0x3655, 0x3960, 0x34cd, 0x350f, 0x3a04, 0x2ca5, 0x3755, 0x3bfd, 0x3bf8, }; -fftval_t output_data_real[128] = { 0x53bf, 0xc31e, 0xb830, 0xc2c1, 0x42a7, 0xc20c, 0xb60e, 0x3835, 0x4542, 0xc090, 0xc44a, 0xc46e, 0x3d03, 0xb7ba, 0xbc84, 0xc26c, 0xad06, 0xc03d, 0x44fc, 0xc324, 0x4172, 0x4083, 0x355d, 0xc658, 0x39b3, 0x368c, 0xbce9, 0x43b3, 0x3bc2, 0x3c3d, 0xb67c, 0x3c11, 0x4150, 0xc72e, 0x42b7, 0xbfb9, 0x45cb, 0x46d6, 0x374a, 0xc454, 0xb243, 0xc466, 0x440d, 0x4847, 0x3a5a, 0x417e, 0x3f24, 0xb0d1, 0x44cb, 0xae38, 0xc1df, 0x1014, 0xc3c0, 0xc521, 0xc041, 0xbcaa, 0x432f, 0xba88, 0xba73, 0xbca0, 0xbfaf, 0x3ad7, 0x38d4, 0xb68e, 0x41c6, 0x411f, 0xbc5d, 0x3aa1, 0xbbb3, 0xba80, 0x3ca6, 0xb990, 0xc434, 0xc1da, 0x3c18, 0xc167, 0x3834, 0x40fd, 0x40b2, 0x44f6, 0x31ae, 0x452b, 0xc11c, 0x3df1, 0xc481, 0x3738, 0xc6d0, 0xc501, 0xbbe7, 0x453a, 0x3ef3, 0xc4f4, 0x40de, 0x375d, 0x2f29, 0xc184, 0x34f6, 0xbe57, 0xc013, 0xbc68, 0x4307, 0x3c28, 0x43af, 0x439f, 0x40dd, 0x38f9, 0x455e, 0x47b3, 0x4347, 0x4344, 0xc0f3, 0x453e, 0x3a31, 0xc3d3, 0x44ba, 0xc1a1, 0x3bf2, 0xc279, 0x3796, 0x3a0d, 0xbca1, 0x42a2, 0xc603, 0x40c1, 0x41b0, 0xc34e, 0xc255, 0x4014, }; -fftval_t output_data_imag[128] = { 0x540b, 0x3996, 0x42da, 0x45aa, 0x3c06, 0xc235, 0x4534, 0x4017, 0xc4a3, 0x4106, 0x3da7, 0xc0ea, 0x45de, 0xc44c, 0x3fe9, 0x3e72, 0x431f, 0xbad2, 0x4394, 0x3c7b, 0xc22a, 0x4451, 0x47e5, 0x45aa, 0xc61c, 0x459f, 0x4459, 0x3958, 0x40a0, 0x4569, 0x3744, 0x4196, 0xc0b1, 0x3cb4, 0xc0bd, 0x42b2, 0x3a7d, 0xc2ef, 0xc402, 0xc224, 0x4558, 0xbc9a, 0x3dee, 0x3fe1, 0xc0b8, 0xc3ab, 0x3c37, 0xc140, 0xc089, 0x4488, 0x4461, 0x3efa, 0x3cb7, 0x45dc, 0xc057, 0xb1fb, 0xc193, 0x49a1, 0x4313, 0x3b60, 0xc180, 0xc0c8, 0x45b2, 0xc049, 0xc27d, 0xc4e2, 0xba90, 0x3ef1, 0xc15a, 0x4168, 0xbe47, 0x3a83, 0xc4cc, 0xba9e, 0xb0eb, 0xc199, 0x40a3, 0x406e, 0xc2ce, 0xb137, 0xc21b, 0x3f03, 0x3fce, 0xc401, 0xc40e, 0x3c3c, 0xb764, 0xc961, 0xbd63, 0x42ad, 0x318c, 0xc300, 0xb783, 0xc6c2, 0x2e77, 0x449c, 0xbdc2, 0xb637, 0xc1d1, 0x3200, 0x4157, 0x46e1, 0xbd03, 0xba6b, 0x37d8, 0xc485, 0x3fed, 0xc476, 0xc093, 0x3a2c, 0x40d7, 0x4147, 0xc3fb, 0xb613, 0x414a, 0xbe05, 0x3d67, 0x46d3, 0xc170, 0x45f8, 0x423b, 0x4603, 0xbcc8, 0x4083, 0xba93, 0xbcf8, 0x3c75, 0xbf85, }; -fftval_t tf_real[128] = { 0x3c00, 0x3bfe, 0x3bf6, 0x3bea, 0x3bd9, 0x3bc3, 0x3ba8, 0x3b88, 0x3b64, 0x3b3b, 0x3b0e, 0x3add, 0x3aa7, 0x3a6d, 0x3a2f, 0x39ed, 0x39a8, 0x395f, 0x3913, 0x38c4, 0x3872, 0x381d, 0x378b, 0x36d7, 0x361f, 0x3564, 0x34a5, 0x33c6, 0x323e, 0x30b2, 0x2e46, 0x2a48, 0x0000, 0xaa48, 0xae46, 0xb0b2, 0xb23e, 0xb3c6, 0xb4a5, 0xb564, 0xb61f, 0xb6d7, 0xb78b, 0xb81d, 0xb872, 0xb8c4, 0xb913, 0xb95f, 0xb9a8, 0xb9ed, 0xba2f, 0xba6d, 0xbaa7, 0xbadd, 0xbb0e, 0xbb3b, 0xbb64, 0xbb88, 0xbba8, 0xbbc3, 0xbbd9, 0xbbea, 0xbbf6, 0xbbfe, 0xbc00, 0xbbfe, 0xbbf6, 0xbbea, 0xbbd9, 0xbbc3, 0xbba8, 0xbb88, 0xbb64, 0xbb3b, 0xbb0e, 0xbadd, 0xbaa7, 0xba6d, 0xba2f, 0xb9ed, 0xb9a8, 0xb95f, 0xb913, 0xb8c4, 0xb872, 0xb81d, 0xb78b, 0xb6d7, 0xb61f, 0xb564, 0xb4a5, 0xb3c6, 0xb23e, 0xb0b2, 0xae46, 0xaa48, 0x8000, 0x2a48, 0x2e46, 0x30b2, 0x323e, 0x33c6, 0x34a5, 0x3564, 0x361f, 0x36d7, 0x378b, 0x381d, 0x3872, 0x38c4, 0x3913, 0x395f, 0x39a8, 0x39ed, 0x3a2f, 0x3a6d, 0x3aa7, 0x3add, 0x3b0e, 0x3b3b, 0x3b64, 0x3b88, 0x3ba8, 0x3bc3, 0x3bd9, 0x3bea, 0x3bf6, 0x3bfe, }; -fftval_t tf_imag[128] = { 0x8000, 0xaa48, 0xae46, 0xb0b2, 0xb23e, 0xb3c6, 0xb4a5, 0xb564, 0xb61f, 0xb6d7, 0xb78b, 0xb81d, 0xb872, 0xb8c4, 0xb913, 0xb95f, 0xb9a8, 0xb9ed, 0xba2f, 0xba6d, 0xbaa7, 0xbadd, 0xbb0e, 0xbb3b, 0xbb64, 0xbb88, 0xbba8, 0xbbc3, 0xbbd9, 0xbbea, 0xbbf6, 0xbbfe, 0xbc00, 0xbbfe, 0xbbf6, 0xbbea, 0xbbd9, 0xbbc3, 0xbba8, 0xbb88, 0xbb64, 0xbb3b, 0xbb0e, 0xbadd, 0xbaa7, 0xba6d, 0xba2f, 0xb9ed, 0xb9a8, 0xb95f, 0xb913, 0xb8c4, 0xb872, 0xb81d, 0xb78b, 0xb6d7, 0xb61f, 0xb564, 0xb4a5, 0xb3c6, 0xb23e, 0xb0b2, 0xae46, 0xaa48, 0x8000, 0x2a48, 0x2e46, 0x30b2, 0x323e, 0x33c6, 0x34a5, 0x3564, 0x361f, 0x36d7, 0x378b, 0x381d, 0x3872, 0x38c4, 0x3913, 0x395f, 0x39a8, 0x39ed, 0x3a2f, 0x3a6d, 0x3aa7, 0x3add, 0x3b0e, 0x3b3b, 0x3b64, 0x3b88, 0x3ba8, 0x3bc3, 0x3bd9, 0x3bea, 0x3bf6, 0x3bfe, 0x3c00, 0x3bfe, 0x3bf6, 0x3bea, 0x3bd9, 0x3bc3, 0x3ba8, 0x3b88, 0x3b64, 0x3b3b, 0x3b0e, 0x3add, 0x3aa7, 0x3a6d, 0x3a2f, 0x39ed, 0x39a8, 0x395f, 0x3913, 0x38c4, 0x3872, 0x381d, 0x378b, 0x36d7, 0x361f, 0x3564, 0x34a5, 0x33c6, 0x323e, 0x30b2, 0x2e46, 0x2a48, }; - -#endif diff --git a/benchmarks/vec-fft/dc_data.c b/benchmarks/vec-fft/dc_data.c deleted file mode 100644 index a913bf0..0000000 --- a/benchmarks/vec-fft/dc_data.c +++ /dev/null @@ -1,14 +0,0 @@ -// See LICENSE for license details. - -int input_data_real[1024] = {1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 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1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576, 1048576}; - -int input_data_imag[1024] = {0, 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335022, 328919, 322803, 316676, 310536, 304385, 298222, 292049, 285864, 279668, 273462, 267246, 261019, 254783, 248537, 242281, 236017, 229744, 223462, 217172, 210873, 204567, 198252, 191931, 185602, 179266, 172923, 166574, 160219, 153858, 147490, 141118, 134740, 128356, 121968, 115576, 109179, 102778, 96373, 89965, 83553, 77138, 70720, 64299, 57876, 51451, 45024, 38595, 32164, 25733, 19300, 12867, 6433, 0, -6433, -12867, -19300, -25733, -32164, -38595, -45024, -51451, -57876, -64299, -70720, -77138, -83553, -89965, -96373, -102778, -109179, -115576, -121968, -128356, -134740, -141118, -147490, -153858, -160219, -166574, -172923, -179266, -185602, -191931, -198252, -204567, -210873, -217172, -223462, -229744, -236017, -242281, -248537, -254783, -261019, -267246, -273462, -279668, -285864, -292049, -298222, -304385, -310536, -316676, -322803, -328919, -335022, -341112, -347190, -353254, -359305, -365343, -371367, -377377, -383373, -389354, -395320, -401272, -407209, -413130, -419036, -424926, -430800, -436658, -442499, -448324, -454131, -459922, -465695, -471451, -477189, -482909, -488611, -494295, -499960, -505606, -511233, -516841, -522429, -527998, -533547, -539075, -544584, -550072, -555539, -560985, -566410, -571814, -577197, -582557, -587896, -593212, -598506, -603778, -609027, -614253, -619456, -624635, -629792, -634924, -640032, -645117, -650177, -655212, -660223, -665209, -670170, -675106, -680016, -684901, -689760, -694593, -699400, -704180, -708934, -713661, -718362, -723035, -727681, -732300, -736891, -741455, -745990, -750498, -754977, -759428, -763850, -768243, -772608, -776943, -781249, -785526, -789773, -793991, -798178, -802336, -806463, -810560, -814626, -818662, -822667, -826641, -830583, -834495, -838375, -842224, -846040, -849825, -853578, -857299, -860988, -864644, -868268, -871859, -875417, -878942, -882434, -885893, -889318, -892710, -896068, -899393, -902684, -905941, -909163, -912352, -915506, -918626, -921711, -924761, -927777, -930757, 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-1036263, -1035260, -1034218, -1033138, -1032019, -1030860, -1029663, -1028427, -1027153, -1025840, -1024488, -1023097, -1021668, -1020201, -1018695, -1017151, -1015569, -1013948, -1012289, -1010592, -1008857, -1007084, -1005273, -1003424, -1001538, -999613, -997651, -995652, -993615, -991541, -989429, -987280, -985094, -982871, -980610, -978313, -975979, -973609, -971201, -968757, -966277, -963760, -961207, -958618, -955993, -953331, -950634, -947901, -945132, -942328, -939488, -936613, -933703, -930757, -927777, -924761, -921711, -918626, -915506, -912352, -909163, -905941, -902684, -899393, -896068, -892710, -889318, -885893, -882434, -878942, -875417, -871859, -868268, -864644, -860988, -857299, -853578, -849825, -846040, -842224, -838375, -834495, -830583, -826641, -822667, -818662, -814626, -810560, -806463, -802336, -798178, -793991, -789773, -785526, -781249, -776943, -772608, -768243, -763850, -759428, -754977, -750498, -745990, -741455, -736891, -732300, -727681, -723035, -718362, -713661, -708934, -704180, -699400, -694593, -689760, -684901, -680016, -675106, -670170, -665209, -660223, -655212, -650177, -645117, -640032, -634924, -629792, -624635, -619456, -614253, -609027, -603778, -598506, -593212, -587896, -582557, -577197, -571814, -566410, -560985, -555539, -550072, -544584, -539075, -533547, -527998, -522429, -516841, -511233, -505606, -499960, -494295, -488611, -482909, -477189, -471451, -465695, -459922, -454131, -448324, -442499, -436658, -430800, -424926, -419036, -413130, -407209, -401272, -395320, -389354, -383373, -377377, -371367, -365343, -359305, -353254, -347190, -341112, -335022, -328919, -322803, -316676, -310536, -304385, -298222, -292049, -285864, -279668, -273462, -267246, -261019, -254783, -248537, -242281, -236017, -229744, -223462, -217172, -210873, -204567, -198252, -191931, -185602, -179266, -172923, -166574, -160219, -153858, -147490, -141118, -134740, -128356, -121968, -115576, -109179, -102778, -96373, -89965, -83553, -77138, -70720, -64299, -57876, -51451, -45024, -38595, -32164, -25733, -19300, -12867, -6433, 0, 6433, 12867, 19300, 25733, 32164, 38595, 45024, 51451, 57876, 64299, 70720, 77138, 83553, 89965, 96373, 102778, 109179, 115576, 121968, 128356, 134740, 141118, 147490, 153858, 160219, 166574, 172923, 179266, 185602, 191931, 198252, 204567, 210873, 217172, 223462, 229744, 236017, 242281, 248537, 254783, 261019, 267246, 273462, 279668, 285864, 292049, 298222, 304385, 310536, 316676, 322803, 328919, 335022, 341112, 347190, 353254, 359305, 365343, 371367, 377377, 383373, 389354, 395320, 401272, 407209, 413130, 419036, 424926, 430800, 436658, 442499, 448324, 454131, 459922, 465695, 471451, 477189, 482909, 488611, 494295, 499960, 505606, 511233, 516841, 522429, 527998, 533547, 539075, 544584, 550072, 555539, 560985, 566410, 571814, 577197, 582557, 587896, 593212, 598506, 603778, 609027, 614253, 619456, 624635, 629792, 634924, 640032, 645117, 650177, 655212, 660223, 665209, 670170, 675106, 680016, 684901, 689760, 694593, 699400, 704180, 708934, 713661, 718362, 723035, 727681, 732300, 736891, 741455, 745990, 750498, 754977, 759428, 763850, 768243, 772608, 776943, 781249, 785526, 789773, 793991, 798178, 802336, 806463, 810560, 814626, 818662, 822667, 826641, 830583, 834495, 838375, 842224, 846040, 849825, 853578, 857299, 860988, 864644, 868268, 871859, 875417, 878942, 882434, 885893, 889318, 892710, 896068, 899393, 902684, 905941, 909163, 912352, 915506, 918626, 921711, 924761, 927777, 930757, 933703, 936613, 939488, 942328, 945132, 947901, 950634, 953331, 955993, 958618, 961207, 963760, 966277, 968757, 971201, 973609, 975979, 978313, 980610, 982871, 985094, 987280, 989429, 991541, 993615, 995652, 997651, 999613, 1001538, 1003424, 1005273, 1007084, 1008857, 1010592, 1012289, 1013948, 1015569, 1017151, 1018695, 1020201, 1021668, 1023097, 1024488, 1025840, 1027153, 1028427, 1029663, 1030860, 1032019, 1033138, 1034218, 1035260, 1036263, 1037226, 1038151, 1039036, 1039883, 1040690, 1041458, 1042186, 1042876, 1043526, 1044137, 1044709, 1045241, 1045734, 1046188, 1046602, 1046977, 1047312, 1047608, 1047865, 1048082, 1048260, 1048398, 1048497, 1048556}; - -int tf_imag[1024] = {0, -6433, -12867, -19300, -25733, -32164, -38595, -45024, -51451, -57876, -64299, -70720, -77138, -83553, -89965, -96373, -102778, -109179, -115576, -121968, -128356, -134740, -141118, -147490, -153858, -160219, -166574, -172923, -179266, -185602, -191931, -198252, -204567, -210873, -217172, -223462, -229744, -236017, -242281, -248537, -254783, -261019, -267246, -273462, -279668, -285864, -292049, -298222, -304385, -310536, -316676, -322803, -328919, -335022, -341112, -347190, -353254, -359305, -365343, -371367, -377377, -383373, -389354, -395320, -401272, -407209, -413130, -419036, -424926, -430800, -436658, -442499, -448324, -454131, -459922, -465695, -471451, -477189, -482909, -488611, -494295, -499960, -505606, -511233, -516841, -522429, -527998, -533547, -539075, -544584, -550072, -555539, -560985, -566410, -571814, -577197, -582557, -587896, -593212, -598506, -603778, -609027, -614253, -619456, -624635, -629792, -634924, -640032, -645117, -650177, -655212, -660223, -665209, -670170, -675106, -680016, -684901, -689760, -694593, -699400, -704180, -708934, -713661, -718362, -723035, -727681, -732300, -736891, -741455, -745990, -750498, -754977, -759428, -763850, -768243, -772608, -776943, -781249, -785526, -789773, -793991, -798178, -802336, -806463, -810560, -814626, -818662, -822667, -826641, -830583, -834495, -838375, -842224, -846040, -849825, -853578, -857299, -860988, -864644, -868268, -871859, -875417, -878942, -882434, -885893, -889318, -892710, -896068, -899393, -902684, -905941, -909163, -912352, -915506, -918626, -921711, -924761, -927777, -930757, -933703, -936613, -939488, -942328, -945132, -947901, -950634, -953331, -955993, -958618, -961207, -963760, -966277, -968757, -971201, -973609, -975979, -978313, -980610, -982871, -985094, -987280, -989429, -991541, -993615, -995652, -997651, -999613, -1001538, -1003424, -1005273, -1007084, -1008857, -1010592, -1012289, -1013948, -1015569, -1017151, -1018695, -1020201, -1021668, -1023097, -1024488, -1025840, -1027153, -1028427, -1029663, -1030860, -1032019, -1033138, -1034218, -1035260, -1036263, -1037226, -1038151, -1039036, -1039883, -1040690, -1041458, -1042186, -1042876, -1043526, -1044137, -1044709, -1045241, -1045734, -1046188, -1046602, -1046977, -1047312, -1047608, -1047865, -1048082, -1048260, -1048398, -1048497, -1048556, -1048576, -1048556, -1048497, -1048398, -1048260, -1048082, -1047865, -1047608, -1047312, -1046977, -1046602, -1046188, -1045734, -1045241, -1044709, -1044137, -1043526, -1042876, -1042186, -1041458, -1040690, -1039883, -1039036, -1038151, -1037226, -1036263, -1035260, -1034218, -1033138, -1032019, -1030860, -1029663, -1028427, -1027153, -1025840, -1024488, -1023097, -1021668, -1020201, -1018695, -1017151, -1015569, -1013948, -1012289, -1010592, -1008857, -1007084, -1005273, -1003424, -1001538, -999613, -997651, -995652, -993615, -991541, -989429, -987280, -985094, -982871, -980610, -978313, -975979, -973609, -971201, -968757, -966277, -963760, -961207, -958618, -955993, -953331, -950634, -947901, -945132, -942328, -939488, -936613, -933703, -930757, -927777, -924761, -921711, -918626, -915506, -912352, -909163, -905941, -902684, -899393, -896068, -892710, -889318, -885893, -882434, -878942, -875417, -871859, -868268, -864644, -860988, -857299, -853578, -849825, -846040, -842224, -838375, -834495, -830583, -826641, -822667, -818662, -814626, -810560, -806463, -802336, -798178, -793991, -789773, -785526, -781249, -776943, -772608, -768243, -763850, -759428, -754977, -750498, -745990, -741455, -736891, -732300, -727681, -723035, -718362, -713661, -708934, -704180, -699400, -694593, -689760, -684901, -680016, -675106, -670170, -665209, -660223, -655212, -650177, -645117, -640032, -634924, -629792, -624635, -619456, -614253, -609027, -603778, -598506, -593212, -587896, -582557, -577197, -571814, -566410, -560985, -555539, -550072, -544584, -539075, -533547, -527998, -522429, -516841, -511233, -505606, -499960, -494295, -488611, -482909, -477189, -471451, -465695, -459922, -454131, -448324, -442499, -436658, -430800, -424926, -419036, -413130, -407209, -401272, -395320, -389354, -383373, -377377, -371367, -365343, -359305, -353254, -347190, -341112, -335022, -328919, -322803, -316676, -310536, -304385, -298222, -292049, -285864, -279668, -273462, -267246, -261019, -254783, -248537, -242281, -236017, -229744, -223462, -217172, -210873, -204567, -198252, -191931, -185602, -179266, -172923, -166574, -160219, -153858, -147490, -141118, -134740, -128356, -121968, -115576, -109179, -102778, -96373, -89965, -83553, -77138, -70720, -64299, -57876, -51451, -45024, -38595, -32164, -25733, -19300, -12867, -6433, 0, 6433, 12867, 19300, 25733, 32164, 38595, 45024, 51451, 57876, 64299, 70720, 77138, 83553, 89965, 96373, 102778, 109179, 115576, 121968, 128356, 134740, 141118, 147490, 153858, 160219, 166574, 172923, 179266, 185602, 191931, 198252, 204567, 210873, 217172, 223462, 229744, 236017, 242281, 248537, 254783, 261019, 267246, 273462, 279668, 285864, 292049, 298222, 304385, 310536, 316676, 322803, 328919, 335022, 341112, 347190, 353254, 359305, 365343, 371367, 377377, 383373, 389354, 395320, 401272, 407209, 413130, 419036, 424926, 430800, 436658, 442499, 448324, 454131, 459922, 465695, 471451, 477189, 482909, 488611, 494295, 499960, 505606, 511233, 516841, 522429, 527998, 533547, 539075, 544584, 550072, 555539, 560985, 566410, 571814, 577197, 582557, 587896, 593212, 598506, 603778, 609027, 614253, 619456, 624635, 629792, 634924, 640032, 645117, 650177, 655212, 660223, 665209, 670170, 675106, 680016, 684901, 689760, 694593, 699400, 704180, 708934, 713661, 718362, 723035, 727681, 732300, 736891, 741455, 745990, 750498, 754977, 759428, 763850, 768243, 772608, 776943, 781249, 785526, 789773, 793991, 798178, 802336, 806463, 810560, 814626, 818662, 822667, 826641, 830583, 834495, 838375, 842224, 846040, 849825, 853578, 857299, 860988, 864644, 868268, 871859, 875417, 878942, 882434, 885893, 889318, 892710, 896068, 899393, 902684, 905941, 909163, 912352, 915506, 918626, 921711, 924761, 927777, 930757, 933703, 936613, 939488, 942328, 945132, 947901, 950634, 953331, 955993, 958618, 961207, 963760, 966277, 968757, 971201, 973609, 975979, 978313, 980610, 982871, 985094, 987280, 989429, 991541, 993615, 995652, 997651, 999613, 1001538, 1003424, 1005273, 1007084, 1008857, 1010592, 1012289, 1013948, 1015569, 1017151, 1018695, 1020201, 1021668, 1023097, 1024488, 1025840, 1027153, 1028427, 1029663, 1030860, 1032019, 1033138, 1034218, 1035260, 1036263, 1037226, 1038151, 1039036, 1039883, 1040690, 1041458, 1042186, 1042876, 1043526, 1044137, 1044709, 1045241, 1045734, 1046188, 1046602, 1046977, 1047312, 1047608, 1047865, 1048082, 1048260, 1048398, 1048497, 1048556, 1048576, 1048556, 1048497, 1048398, 1048260, 1048082, 1047865, 1047608, 1047312, 1046977, 1046602, 1046188, 1045734, 1045241, 1044709, 1044137, 1043526, 1042876, 1042186, 1041458, 1040690, 1039883, 1039036, 1038151, 1037226, 1036263, 1035260, 1034218, 1033138, 1032019, 1030860, 1029663, 1028427, 1027153, 1025840, 1024488, 1023097, 1021668, 1020201, 1018695, 1017151, 1015569, 1013948, 1012289, 1010592, 1008857, 1007084, 1005273, 1003424, 1001538, 999613, 997651, 995652, 993615, 991541, 989429, 987280, 985094, 982871, 980610, 978313, 975979, 973609, 971201, 968757, 966277, 963760, 961207, 958618, 955993, 953331, 950634, 947901, 945132, 942328, 939488, 936613, 933703, 930757, 927777, 924761, 921711, 918626, 915506, 912352, 909163, 905941, 902684, 899393, 896068, 892710, 889318, 885893, 882434, 878942, 875417, 871859, 868268, 864644, 860988, 857299, 853578, 849825, 846040, 842224, 838375, 834495, 830583, 826641, 822667, 818662, 814626, 810560, 806463, 802336, 798178, 793991, 789773, 785526, 781249, 776943, 772608, 768243, 763850, 759428, 754977, 750498, 745990, 741455, 736891, 732300, 727681, 723035, 718362, 713661, 708934, 704180, 699400, 694593, 689760, 684901, 680016, 675106, 670170, 665209, 660223, 655212, 650177, 645117, 640032, 634924, 629792, 624635, 619456, 614253, 609027, 603778, 598506, 593212, 587896, 582557, 577197, 571814, 566410, 560985, 555539, 550072, 544584, 539075, 533547, 527998, 522429, 516841, 511233, 505606, 499960, 494295, 488611, 482909, 477189, 471451, 465695, 459922, 454131, 448324, 442499, 436658, 430800, 424926, 419036, 413130, 407209, 401272, 395320, 389354, 383373, 377377, 371367, 365343, 359305, 353254, 347190, 341112, 335022, 328919, 322803, 316676, 310536, 304385, 298222, 292049, 285864, 279668, 273462, 267246, 261019, 254783, 248537, 242281, 236017, 229744, 223462, 217172, 210873, 204567, 198252, 191931, 185602, 179266, 172923, 166574, 160219, 153858, 147490, 141118, 134740, 128356, 121968, 115576, 109179, 102778, 96373, 89965, 83553, 77138, 70720, 64299, 57876, 51451, 45024, 38595, 32164, 25733, 19300, 12867, 6433}; - diff --git a/benchmarks/vec-fft/fft-data-gen b/benchmarks/vec-fft/fft-data-gen deleted file mode 100755 index a8a14d0..0000000 --- a/benchmarks/vec-fft/fft-data-gen +++ /dev/null @@ -1,84 +0,0 @@ -#!/usr/bin/env python - -import sys -import numpy - -def array_print(name, data): - if type_scalar == numpy.float16: - a = ['{:#04x}'.format(h.astype(int)) for h in data.view(dtype=numpy.uint16)] - else: - a = [repr(x) for x in data] - print 'fftval_t {}[{}] = {{ {} }};'.format(name, len(a), ', '.join(a)) - -def array_permute(data, radix = 2): - logradix = int(numpy.log2(radix)) - term_mask = int(radix - 1) -# num_term = int(numpy.log2(len(data)) / logradix) - for i in xrange(0, len(data)): - # Obtain permuted address - i_left = i - permuted = 0 - cur_fft_size = radix - while cur_fft_size <= len(data): - permuted = (permuted << logradix) | (i_left & term_mask) - i_left >>= logradix - cur_fft_size <<= logradix - # Permute only once and when addresses are different - if i < permuted: - tmp = data[i] - data[i] = data[permuted] - data[permuted] = tmp - -fft_size = 1024 -type_scalar = numpy.float16 -permute = True - -if len(sys.argv) > 1: - type_scalar = { - '16' : numpy.float16, - '32' : numpy.float32, - '64' : numpy.float64 }.get(sys.argv[1].strip(), None) - if type_scalar == None: - sys.exit('Invalid datatype') - -if len(sys.argv) > 2: - fft_size = sys.argv[2].strip() - if not fft_size.isdigit(): - sys.exit('Invalid FFT size') - fft_size = int(fft_size) - -numpy.random.seed(seed=0) - -print '#include "fft_const.h"' - -# Generate input data -input_real = numpy.random.uniform(size=fft_size).astype(type_scalar) -input_imag = numpy.random.uniform(size=fft_size).astype(type_scalar) - -# Compute reference FFT output -type_cmplx = numpy.complex128 if (type_scalar == numpy.float64) else numpy.complex64 -input_cmplx = input_real.astype(type_cmplx) -input_cmplx.imag = input_imag -output_cmplx = numpy.fft.fft(input_cmplx) - -if permute: - array_permute(input_real) - array_permute(input_imag) - -array_print('input_data_real', input_real) -array_print('input_data_imag', input_imag) - -output_real = output_cmplx.real.astype(type_scalar) -output_imag = output_cmplx.imag.astype(type_scalar) - -array_print('output_data_real', output_real) -array_print('output_data_imag', output_imag) - -# Generate twiddle factors (TFs) -# Negate sine since twiddle factor angles are generated *clockwise* from 0 -rad = [(2.0 * numpy.pi * (float(i) / fft_size)) for i in xrange(fft_size)] -tf_real = numpy.cos(rad).astype(type_scalar) -tf_imag = -numpy.sin(rad).astype(type_scalar) - -array_print('tf_real', tf_real) -array_print('tf_imag', tf_imag) diff --git a/benchmarks/vec-fft/fft_const.h b/benchmarks/vec-fft/fft_const.h deleted file mode 100644 index c9e30ea..0000000 --- a/benchmarks/vec-fft/fft_const.h +++ /dev/null @@ -1,71 +0,0 @@ -// See LICENSE for license details. - -#ifndef __FFT_CONST_H -#define __FFT_CONST_H - -#ifndef FFT_SIZE -#define FFT_SIZE 1024 -#endif /* FFT_SIZE */ - -#if 0 - #define FFT_FIXED - #define DATA_IN_PERMUTED -#else -// #define DATA_IN_UNPERMUTED - #define FFT_FLOATING - #define FFT_FLOATING_PREC 64 -#endif - -#if defined(FFT_FIXED) - #define FIX_PT 20 - #define DATA_WIDTH 32 -#elif defined(FFT_FLOATING) - #if FFT_FLOATING_PREC == 16 - #define FP_HALF - #elif FFT_FLOATING_PREC == 32 - #define FP_SINGLE - #elif FFT_FLOATING_PREC == 64 - #define FP_DOUBLE - #else - #error "Unsupported floating-point configuration" - #endif - #define DATA_WIDTH FFT_FLOATING_PREC -#else - #error "Define fixed or floating point in fft_const.h" -#endif - -#if !defined(__ASSEMBLY__) - -#include -#include - -#if defined(FFT_FIXED) - typedef int fftval_t; - typedef int fftbit_t; - #define FFT_PRI "%08x" -#elif defined(FFT_FLOATING) - #if defined(FP_HALF) - typedef uint16_t fftval_t; - typedef uint16_t fftbit_t; - #define FFT_PRI "%04" PRIx16 - #elif defined(FP_SINGLE) - typedef float fftval_t; - typedef uint32_t fftbit_t; - #define FFT_PRI "%08" PRIx32 - #elif defined(FP_DOUBLE) - typedef double fftval_t; - typedef uint64_t fftbit_t; - #define FFT_PRI "%016" PRIx64 - #endif -#endif - -extern fftval_t input_data_real[FFT_SIZE]; -extern fftval_t input_data_imag[FFT_SIZE]; -extern fftval_t output_data_real[FFT_SIZE]; -extern fftval_t output_data_imag[FFT_SIZE]; -extern fftval_t tf_real[FFT_SIZE]; -extern fftval_t tf_imag[FFT_SIZE]; - -#endif /* __ASSEMBLY__ */ - -#endif /* __FFT_CONST_H */ diff --git a/benchmarks/vec-fft/fft_cos_data.c b/benchmarks/vec-fft/fft_cos_data.c deleted file mode 100644 index 909e0ba..0000000 --- a/benchmarks/vec-fft/fft_cos_data.c +++ /dev/null @@ -1,8 +0,0 @@ -// See LICENSE for license details. - -float input_data_real[ 1024 ] = { 1.0, 0.999981175283, 0.999924701839, 0.999830581796, 0.999698818696, 0.999529417501, 0.999322384588, 0.999077727753, 0.998795456205, 0.998475580573, 0.9981181129, 0.997723066644, 0.997290456679, 0.996820299291, 0.996312612183, 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-#include "fft_const.h" - -int log2down(int in) -{ - int counter = -1; - while(in > 0) { counter++; in = in >> 1; } - return counter; -} - -void fft(fftval_t workspace_real[], fftval_t workspace_imag[], - const fftval_t tf_real[], const fftval_t tf_imag[]) //size is FFT_SIZE -{ - const int num_stage_ops = FFT_SIZE >> 1; - const int logfftsize = log2down(FFT_SIZE); - - int given_vl; - // First, setup hwacha to what we need: -#if defined(FFT_FIXED) - // num_stage_ops VL, 9 x-reg (1 zero, 2 ctrl, 4 data, 2 scratch), 1 fpu (avert bug) - asm volatile ("vsetcfg 9, 1"); -#elif defined(FFT_FLOATING) - asm volatile ("vsetcfg 8, 6"); - #if defined(FP_SINGLE) -// asm volatile ("vsetprec 32"); - #elif defined(FP_HALF) -// asm volatile ("vsetprec 16"); - #elif defined(FP_DOUBLE) - #else - #error wat - #endif -#endif - asm volatile ("vsetvl %[gvl], %[nvl]" : [gvl]"=r"(given_vl) : [nvl]"r"(num_stage_ops)); - asm volatile ("fence"); // Make sure prefilling of workspace is complete - - for(int stage = 0; stage < logfftsize; stage++) - { - const int half_cur_fft_size = (1 << stage); - const int sel_block_op = half_cur_fft_size-1; - const int sel_block = ~sel_block_op; - const int tf_scale = logfftsize - stage - 1; - - // Stripmining loop - for(int lane_start = 0; lane_start < num_stage_ops; lane_start += given_vl) - { - // Setup new vector length for this stripmining pass - const int needed_vl = num_stage_ops - lane_start; - asm volatile ("vsetvl %[gvl], %[nvl]" : [gvl]"=r"(given_vl) : [nvl]"r"(needed_vl)); - -#if defined(FFT_FIXED) - // First VF block to have vector unit determine what op it is doing - asm volatile (R"( - vmsv vx1, %[lane_start] - vmsv vx2, %[sel_block] - vmsv vx3, %[sel_block_op] - vmsv vx4, %[tf_scale] - vmsv vx5, %[half_cfs] - vf 0(%[vf_ptr]) - )": // no output registers - : [lane_start]"r"(lane_start), - [sel_block]"r"(sel_block), - [sel_block_op]"r"(sel_block_op), - [tf_scale]"r"(tf_scale), - [half_cfs]"r"(half_cur_fft_size), - [vf_ptr]"r"(&vf_fft_init) - : // no clobber - ); - - // Second VF block loads tf and op2 then calculates scale factor - asm volatile (R"( - vmsv vx4, %[tf_real] - vmsv vx5, %[tf_imag] - vmsv vx6, %[workspace_real] - vmsv vx7, %[workspace_imag] - vmsv vx8, %[fix_pt] - vf 0(%[vf_ptr]) - )": // no output registers - : [tf_real]"r"(tf_real), - [tf_imag]"r"(tf_imag), - [workspace_real]"r"(workspace_real), - [workspace_imag]"r"(workspace_imag), - [fix_pt]"r"(FIX_PT), - [vf_ptr]"r"(&vf_fft_scale) - : // no clobber - ); -#elif defined(FFT_FLOATING) - // First VF block to have vector unit determine what op it is doing - asm volatile (R"( - vmsv vx1, %[lane_start] - vmsv vx2, %[sel_block] - vmsv vx3, %[sel_block_op] - vmsv vx4, %[tf_scale] - vmsv vx5, %[half_cfs] - vf 0(%[vf_ptr]) - )": // no output registers - : [lane_start]"r"(lane_start), - [sel_block]"r"(sel_block), - [sel_block_op]"r"(sel_block_op), - [tf_scale]"r"(tf_scale), - [half_cfs]"r"(half_cur_fft_size), - [vf_ptr]"r"(&vf_fft_init) - : // no clobber - ); - - // Second VF block loads tf and op2 then calculates scale factor - asm volatile (R"( - vmsv vx4, %[tf_real] - vmsv vx5, %[tf_imag] - vmsv vx6, %[workspace_real] - vmsv vx7, %[workspace_imag] - vf 0(%[vf_ptr]) - )": // no output registers - : [tf_real]"r"(tf_real), - [tf_imag]"r"(tf_imag), - [workspace_real]"r"(workspace_real), - [workspace_imag]"r"(workspace_imag), - [vf_ptr]"r"(&vf_fft_scale) - : // no clobber - ); -#else - #error no mode selected in vec-fft/vec-fft.c -#endif - - // Third VF block actually calculates the results - asm volatile (R"( - vmsv vx5, %[workspace_real] - vmsv vx6, %[workspace_imag] - vf 0(%[vf_ptr]) - )": // no output registers - : [workspace_real]"r"(workspace_real), - [workspace_imag]"r"(workspace_imag), - [vf_ptr]"r"(&vf_fft_exec) - : // no clobber - ); - - // Fourth VF block stores first result - asm volatile (R"( - vmsv vx3, %[workspace_real] - vmsv vx4, %[workspace_imag] - vf 0(%[vf_ptr]) - )": // no output registers - : [workspace_real]"r"(workspace_real), - [workspace_imag]"r"(workspace_imag), - [vf_ptr]"r"(&vf_fft_store1) - : "memory" - ); - - // Fifth VF block stores second result - asm volatile (R"( - vmsv vx3, %[workspace_real] - vmsv vx4, %[workspace_imag] - vf 0(%[vf_ptr]) - )": // no output registers - : [workspace_real]"r"(workspace_real), - [workspace_imag]"r"(workspace_imag), - [vf_ptr]"r"(&vf_fft_store2) - : "memory" - ); - - } - } - - asm volatile ("fence"); // Make sure all that work from vector unit is visible to CPU - - return; -} diff --git a/benchmarks/vec-fft/vec-fft.h b/benchmarks/vec-fft/vec-fft.h deleted file mode 100644 index 7656cbc..0000000 --- a/benchmarks/vec-fft/vec-fft.h +++ /dev/null @@ -1,21 +0,0 @@ -// See LICENSE for license details. - -#ifndef __VEC_FFT_H -#define __VEC_FFT_H - -#include "fft_const.h" - -// Simple C version - -int log2down(int in); -void fft(fftval_t workspace_real[], fftval_t workspace_imag[], const fftval_t tf_real[], const fftval_t tf_imag[]); - -// VF blocks - DO NOT CALL FROM SCALAR CORE -extern void vf_test(); -extern void vf_fft_init(); -extern void vf_fft_scale(); -extern void vf_fft_exec(); -extern void vf_fft_store1(); -extern void vf_fft_store2(); - -#endif /* __VEC_FFT_H */ diff --git a/benchmarks/vec-fft/vec-fft_gaussian.c b/benchmarks/vec-fft/vec-fft_gaussian.c deleted file mode 100644 index a8c1e09..0000000 --- a/benchmarks/vec-fft/vec-fft_gaussian.c +++ /dev/null @@ -1,14 +0,0 @@ -// See LICENSE for license details. - -int input_data_real[1024] = {-896054, 949431, -1181578, 253232, -258369, -152000, 619625, -76677, 465711, -549326, -886958, -966940, 642303, -1412490, 762634, -220791, -1315319, -2559848, 1722557, -1279554, -784697, -85712, -470933, -2785179, -66578, -1597429, -409911, 896, 1027796, 48085, 1774527, 562113, 1795654, 983044, -60377, -1573581, 1030270, -773291, -987375, -291152, 1126075, -406236, -630897, 1531200, 153252, -1544032, 518357, -479677, -489022, 768468, 216657, 978756, 60305, 323742, -266762, -1654684, 1162783, 367356, -215242, 77760, 584574, 352846, -1205031, 202189, 12621, -777742, 1241171, -353489, -201242, 268114, 7405, 511548, 594019, 1378269, -470360, -1419079, -2068041, -224985, 773760, -133786, 166345, 56818, -329117, 710806, -406329, -325712, -1090084, 70838, 1004493, 716570, 1557742, 1814687, -1044653, 865660, 423172, 280485, 122644, 1599035, 836955, -966475, -731759, -1342635, -918704, -478514, -1729195, -275916, 1481397, -80107, -320867, 1571394, 441358, 1095253, 123305, 515740, 558500, 735220, -1409019, -192480, 750830, -385698, -133846, 582203, -538534, 906199, 448649, -1011173, 1112875, 305645, -427417, -1621730, -771200, -807072, -1648200, 2275694, -250040, 166780, 75114, 1498792, -852391, -1449432, 387756, 590382, 630725, 1111966, -1463601, 1379964, 588656, 36544, 585505, -675475, -1147007, 122834, -2281502, 1148931, 840446, -1322731, 2822403, 164183, 799482, 212823, -1077917, -2276541, -2416247, -1866483, 25406, -532814, -28766, -3399, -229289, -884731, -697664, 1388647, 1413131, 695668, 1600785, 1053622, 1882168, 807694, 1496109, 414407, -354594, 852655, -726330, -760018, 203035, 861991, 2077817, -278761, -1692805, -163980, 152551, 99640, -1544466, 424749, 600022, -224627, 1700150, 257985, -710227, -653561, -278079, 65958, 536047, -514225, 131065, 1879774, 1325692, -418569, -94234, -1567061, -1329031, -185396, 321072, -576789, -2082050, 120663, -1112296, -526319, 763200, -26381, 1324391, -740749, 173611, -1034909, -400867, -599852, -854975, 506465, -470497, -1690555, -599600, -774910, 480166, -551595, -154846, 1148952, -531685, -1420372, 115244, -44897, 224230, -235359, -491645, 580113, -930422, -1959150, 660689, -312934, -775785, -1447388, -738147, 327008, 117518, -1024839, -742963, 1113591, 512088, 981759, 224251, 879687, 530700, 793549, -1133250, -1984799, -201157, -226046, -693217, 1865422, -1323405, 727875, 1099706, -572954, 876134, 5546, -359252, -1477340, -1827760, 1425401, -713946, 407302, 296915, 428736, -1928924, 199630, -268383, 524386, -954547, -1009395, -299817, -310362, -3118676, 619580, 274035, -291538, 10998, 54373, -2682711, 1059473, 1900561, -1072897, 390315, 553662, 286722, -575054, 291089, -324509, -2201875, -1739589, -592230, -2358024, 1035206, 101656, 51362, -161931, 982101, 1972023, -940406, 117267, 919302, 706673, -526962, 3251470, -70727, 1354903, -123238, 191080, 2197403, -907972, -1631270, -273662, -43394, 100110, -1757122, 424462, -318587, 241805, -1161233, -766219, -844215, -424058, -571869, 1058981, -576705, -69864, 786586, 3420949, 1175440, -1369774, -1033382, 1895799, -160257, -500482, 649412, 523523, 1044180, 455826, 604125, 781678, -35555, -380257, -2101152, -2052395, 1345031, -1749075, -1898768, 2596126, 877930, 886063, -1747101, 361069, -2709924, -387654, 1461459, 278642, 284030, -2189727, -579640, -410905, 1800776, -387552, -616487, -891888, 1293689, 544185, 165521, -746200, 25612, -748496, -693907, 440270, -1355509, 802877, -226185, -122957, -163764, 706156, -599130, 2085773, 687121, 1536468, -197261, -65999, -602517, -1996625, 711481, 558923, 1575241, -131589, 1443891, 853304, 1450518, 2433068, -614678, 902956, 276921, -865560, 1250774, 1178148, 1627304, -526388, -293789, 163521, -2227160, -1681836, 1054701, -2316942, -575982, -220544, -907539, -728331, -149547, -309108, 1339888, -698216, 333701, 437526, 2094829, -1361341, -461547, 1162315, 1493649, -1052221, 403851, 841804, 2322413, 271887, 1100268, 954880, 97292, 638758, 300629, 654241, -1190910, -141642, 709317, -1761989, -1445740, 1071331, 1503261, -492201, -975276, 730555, -450130, -678104, -690089, -1439162, 226482, -48190, 977167, -403028, -660667, 602354, -970278, 376586, 1099863, -537913, 627956, -71364, -819583, -116110, 114762, 1227038, -416023, 1263602, 419692, 1489545, -323662, 57509, 148590, -627405, -1416122, -994706, -1207921, 2849186, 87464, 38164, -790326, -810378, 917028, -1707856, -782588, 39726, 1311549, 476992, 121776, -5966, -1107219, -113871, -1836494, 292648, 782507, -327742, 1568375, 1031082, 875287, -949597, -364015, -1345238, 2049161, 1199569, -1566459, 432513, -697595, -1989664, 117455, -298029, -372192, -278563, 785990, -307587, 2308882, -128000, 853709, -469916, 569248, -1013809, -92453, -612595, -976635, 407757, -278549, -553747, -1127594, 35556, -967385, -1254461, 2458671, -1235129, 112282, -7618, 1232264, -1584499, 546417, 636949, -788087, 204249, 563736, 905080, 24683, -772095, 957269, -476610, 3997491, -1132151, -87573, -1925741, 423206, 1759035, 345800, -1505568, 857837, 1280631, 672655, 1133353, -2360246, -310429, 1471262, 1874920, -942267, -494638, -1092077, -10703, -798528, 291551, 195560, 603693, 485551, -37890, -681278, 1318510, -1775936, -267078, -1193401, -626711, 427957, -977820, 1177448, -1891652, -486457, -1858903, -251575, 1087978, -1625087, 298155, -1557769, 1112788, 1633070, 742091, 750361, 717342, -597939, -393911, -348514, 1606463, 1104431, -1780884, -1724355, -1087455, -626704, -234591, -841, 595062, -210024, -1150164, 298276, -1357687, 1092760, -795133, 437956, -1073763, -541, -1756437, -423091, -135638, -501750, 1843207, -499411, 515043, -347171, -1864412, 2081029, 935757, -1217682, -862780, 643680, -1682284, 1052595, -1055351, 1278938, -2296045, 728516, -1328562, 316609, -503151, -1317546, -310576, -821390, 717855, -447765, -82472, 226472, -2007236, 1839585, -908416, -131113, 61112, -439936, 37521, -56853, -322043, -537081, -1305022, 613039, -398354, -2251352, -274268, 213708, 1216898, -145297, 163831, 802134, 616814, 742237, 71663, -181725, -234834, 1567310, -433700, 1143683, 1217074, 588362, 880977, 257134, -251325, 419032, 1358747, -1010892, 911781, -114881, 1358209, 1938967, 2496063, 643557, 1131044, 1215299, -1293521, -552701, 535820, -59013, -364820, 401230, -493578, 934606, 947383, 90222, -982021, 823033, -767065, 719868, 555083, -542885, -248389, 683906, -1000980, 960526, 379686, -1332005, 3005752, -1014656, -707705, 957653, 1395720, 695949, -2199684, -1472357, -1402525, -1056170, -773175, -1038523, -1648483, 439225, -604068, 323281, 990838, -258093, -642187, 638228, 1016123, 1215852, -755431, -791548, 232428, -82638, 420739, -1182173, 2073021, -190956, -1426757, 1310320, -529883, 905258, 232249, -107927, -778138, -739516, 819476, 380856, 324304, 750739, -85899, -224870, 2741555, 241328, -1001409, 410347, -803508, 1603523, 83407, -1310198, -841961, -1499826, -231665, -1204370, 365869, 657035, -870479, -947226, 41541, 53460, 1185594, 197060, -442508, 560089, -648000, -1789746, 199013, 792625, 983644, -1255249, 611407, -642979, 2761, 1029260, 165283, -346945, -1241505, -1867499, -330354, 453762, 1144514, 1677530, -794614, -113484, 93134, 174381, 91979, -1072786, 546927, -950065, -1068562, -1316833, 2010054, 1167861, 376645, -1598679, -330354, -64535, -439935, 108686, -122528, -816010, -1657702, 1640815, -729089, -2109620, -1544674, 1751899, 828989, 1396845, -840295, 807944, -1422573, -1962193, -1494306, 1100314, -1035079, -113884, -755568, 311640, 21811, 1118977, 1769466, 272869, 1483856, -2397511, -1212979, -1870837, 66655, -844513, 566095, 258971, -2441991, -53408, 2379521, 1579490, 94538, -1729911, -2271954, -92893, -57722, 755889, 971922, 61839, 1289233, -1708188, 429444, 329090, -846816, -1406843, -329808, -487371, -1342151, -7656, 2160620, 1048363, -1481379, -1973413, 89442, -863813, -334120, 2920250, 1679680, -203732, -840043, 812270, -1065058, 1000115, -1755099, 1098146, -206412, -352184, 45945, -2653853, 539338, -217170, -25474, -1541171, -640479, -1465498, -590507, -294424, 1133931, -258876, -1336660, -36708, -136578, 274059, 2340197, -1661670, -569377, 11224, -781516, 1231584, 2084167, 647286, 1491175, 1359026, 1980953, -529280, 326660, 833554, 1246125, -1181280, -440724, -999991, -1751126, -1058615, 1202373, 379613, -94962, -548041, -2378721, 340897, 1644642, 384925, 10212, -1439416, 1377793, 1736966, -677616, -185008, 1062970, 334065, -923961, 1591540, -323994, 1729168, 1105046, -261575, -256889, 417819, 591476, -1039900, -873951, 299386, -365, -574062, -12822, 773415, -1887046, 1720955, 401646, 903317, 843614, 24321, 397914, -517594, -966687, 1225655, 1041758, 1609662, 530653, 2082272, 379586, -653861, -1324874, -543320, -902844, -156747, 314204, -221853, 698115, 2373708, -473267, -867591, 1789907, 50399, 148680, 110642, 2565631, 1338325, 1122299, -771531, -434336, 962718, -417205, 325343, 221979, -432146, 2039328, -496594, 646733, 707371, -555182, -499570, -1122461, 70865, -267403, -21031, 967469, 515973, 1838992, 1806965, -118340}; - -int input_data_imag[1024] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - -int output_data_real[1024] = {-12552904, 900359, 13572614, 6612100, 21544345, 11727877, 41132063, 19376007, 28943753, -27164137, -33144128, 6308054, -4036209, 5075419, 61637708, -7000522, 10258235, -3290422, -1930761, -34401327, 11137064, 7072560, -5882191, -220280, 23820092, -2747162, -28342204, 3125936, 7067612, -29776710, 55435764, -17075007, -19174432, 20671700, -12850843, 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50925957, 19428607, -20411834, 12547811, -1014932, 10278862, -32309319, -1845021, -1849277, -45728792, 2285470, 35351079, 4290917, -30853329, -8422261, -36146114, 27125965, -17918864, -3137631, 16473491, 4954133, -15439592, 17157868, -18076982, -34202615, -18793524, -10174558, -2904950, 11985992, -44150120, -35036737, 21105041, 20053489, -1150444, 5200899, -9805414, -23632872, -9796924, -17291839, -12551635, -16640164, -6028118, -12190830, -10279820, -883003, 3527116, 40755752, 28098784, -7167611, 5362554, -41423374, 24889496, 47850412, 12089976, -37773935, -18754709, 46972743, 22713778, -16370229, 26601571, 6009203, -23452807, -11836470, 43211515, 20586799, 33670875, -50098827, 38216755, 3992212, -48197762, 10221413, -4180759, 38877047, 24300809, 29759474, -3046819, -24536720, 36519832, -32126982, 48288800, -35312888, 609558, -47953658, -37884802, 25200530, 4336904, 1479356, -7797884, -18955924, -32376585, -21405801, 29384571, -24481459, 2543253, 17158726, -2776591, 11240742, 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6612100, 13572614, 900359}; - -int output_data_imag[1024] = {0, -5173739, 8732116, -9198791, 14335177, 438680, -22709701, -17845044, 46347274, -6345647, -2448769, -3536186, -11317514, -6755869, -56193258, 20510638, 36621773, 15143807, -23048336, -38525115, -34883897, 24214333, -25231715, -12107006, 713935, -26002012, 9793100, 27093766, 4897309, -15653296, 10724876, -29977588, 4309154, 23693365, -7664895, -45459513, 23194556, -2303636, 1369664, 2909709, -27032265, 20630463, -6235213, -2795181, -11657347, -56308552, -20811426, -35038296, 17912124, -14484060, -6781618, -38557643, -19148006, 35906257, 48027176, -21283279, 40736471, -11382928, 38262486, 12787192, -23033012, -8422805, -5377539, 22253959, -30745831, -29877218, -4239294, -28422500, -3618200, 13973117, 29741342, -17022267, -1957036, 8899885, 15742866, -33238888, 10084317, 26605444, 1030161, -21185160, -34935187, -16030047, 3642533, -34366997, 1826498, 29308452, -25112834, 20471937, -1180009, 37130194, -38361361, -15382227, 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-15345780, -12994147, -21208035, -25026091, -11433931, 15909594, -15057552, 4344815, 16416258, -19924616, -25098907, -15034316, 7031513, -9625884, -35247437, 2958647, 34044834, -47596541, 30806704, 31809436, -51382701, -109428, -30027525, -2742560, -12145827, 17664073, 7117373, -26213934, 0, 26213934, -7117373, -17664073, 12145827, 2742560, 30027525, 109428, 51382701, -31809436, -30806704, 47596541, -34044834, -2958647, 35247437, 9625884, -7031513, 15034316, 25098907, 19924616, -16416258, -4344815, 15057552, -15909594, 11433931, 25026091, 21208035, 12994147, 15345780, -8759873, 25633029, 44738518, -31706075, 44529567, 28238711, 17486541, 62195634, -32974224, 78381147, 20509584, -56712, 29467733, 22061171, 7143287, -31088721, 14083491, 31373984, -165948, -15671217, 6831406, 21414293, -6868965, 16681977, 396690, -15436341, -19937687, 1383770, 29337748, -40726766, -14754701, 36847561, 26369806, 490345, -39589659, -14034699, -5721295, -39065223, 8501137, 40546139, -34778357, -12270149, -6564701, 41201403, 23646294, -21125488, -33718206, 57146386, 5799578, -13056624, 16238838, -12409669, -10854482, 13884018, -4152182, -20569560, 2701802, 18259021, -10880345, -532791, -13007038, -10768143, 22031772, -35820807, 30512620, 11082589, 43129459, -10314988, -3674016, 24915723, -27274726, -21680350, 1198627, 3928810, 5449065, 12591531, 18229998, -36752501, -39941609, -7983744, 38196573, -7260622, 28832233, -5736405, 8147370, 30108011, 7546326, -14880233, -3420438, 19766821, -36134613, -6212685, 10847049, 5342012, -19138174, 17323815, 26033484, -13570431, 15345862, -20620814, 15553962, -19934345, 1606887, -14628346, -29271928, -2846524, 38962700, -11808656, -29344316, -4349653, -10924238, -20165657, 32018696, 1341850, -13438166, -4585861, -3022892, -32175079, -6147806, -26307468, -21036639, -6260154, -3608809, -28757001, 6927380, 12194598, -34724033, -30547368, 31225530, -1477466, -12167718, 23099501, -21514861, 21540809, -33958782, 21068700, -5877933, 15688654, 5924909, 33678728, 2280056, 9215526, -15514221, 32164669, -5509349, 43765857, -9032313, -6224865, 38654097, 7896995, -7041401, -18122433, 35782940, -30171442, -17047542, -14160197, -23502922, -18988939, 22804081, -25405396, 41407616, -536487, -9721116, 8151529, -23027632, -26241701, 28571608, 5015656, 16314336, 9029718, 14876678, 19087027, -8554116, -4166791, 20680408, -63722083, 9366616, 16829798, -39939458, -32260023, 2542801, 11304099, -1198608, -44653591, 13641011, -21909223, -3171432, -6448906, 18683886, 25016094, 8709757, 3278485, -11729869, -13130115, -5602343, -33578834, -14694942, 13125160, -6396874, 33500087, -9433003, 41081131, -21665127, 25322923, 41817568, -3051905, 1433333, 10858236, -12327567, 41073536, 26127426, 22093506, 32857246, 17494763, 10110669, -36609737, 2942996, -11104819, -26476785, -30931967, 37462363, -11922939, 12237932, 9026632, -25470858, -9112167, 8082453, -8747460, -50315786, 8782034, 22775001, -37769763, -38490970, 536372, 40891318, 36509740, -30714238, 45195789, 12321691, 24413730, 51927238, 24457742, -29577848, 20050130, 17752896, -26381932, 14941794, 45409365, -20977257, 8391765, 3175589, -37530144, 30533556, 45328150, -36482875, 5628499, -21857252, -28322835, 11849460, -30214820, -58484885, 44358772, 32709009, -25373350, 50712873, 16549930, -4574152, -4895114, -14736647, 59800506, -19631795, -21028590, -25686170, -14133732, 24041184, -4900205, 18673224, 53074519, -3596058, 6969494, 16237695, -60085554, -5224738, 22256630, -1897870, -5968061, 21900938, -10868795, -2844196, 4176864, 96265292, -15988251, 12876619, -8257865, -32515341, -5324160, -8975377, -18336350, 20954012, -4284503, 18109048, -28945096, 4618667, 26936877, -8617025, -9267318, -5589150, 35858488, -8713693, -37945215, 14892223, 51497130, 41648342, -34292210, 10850678, -9870059, 27036248, 38503205, 15693435, -34294230, 2667905, -16965458, 31433357, 8466738, 18952889, 22200939, 16457884, 32790484, -12597726, -16044736, -21313758, 10111916, -28005433, 30525619, 18433286, 16313096, -32233478, 9180479, -26992838, -7735047, -13724852, 3312496, 17607802, -8780329, -11074125, 11301906, -42470495, 37542741, 9842343, -9835530, 21226148, 10179497, 20312309, -1747345, -31593825, -51741722, -44020436, 11661418, 10970839, -25734336, -2750861, 28257394, 30033796, 33870140, -3150296, 30709790, -14438956, -53294091, -43285275, -6280980, 8531371, 12405219, -11739988, 1645052, -970002, -12116931, 17880023, -35488914, 240613, -3116624, -15030263, -14599232, 19604410, 33459044, 8987923, 2200086, -14969775, -8415830, 10001075, -51939635, 10901236, 28458875, 15382227, 38361361, -37130194, 1180009, -20471937, 25112834, -29308452, -1826498, 34366997, -3642533, 16030047, 34935187, 21185160, -1030161, -26605444, -10084317, 33238888, -15742866, -8899885, 1957036, 17022267, -29741342, -13973117, 3618200, 28422500, 4239294, 29877218, 30745831, -22253959, 5377539, 8422805, 23033012, -12787192, -38262486, 11382928, -40736471, 21283279, -48027176, -35906257, 19148006, 38557643, 6781618, 14484060, -17912124, 35038296, 20811426, 56308552, 11657347, 2795181, 6235213, -20630463, 27032265, -2909709, -1369664, 2303636, -23194556, 45459513, 7664895, -23693365, -4309154, 29977588, -10724876, 15653296, -4897309, -27093766, -9793100, 26002012, -713935, 12107006, 25231715, -24214333, 34883897, 38525115, 23048336, -15143807, -36621773, -20510638, 56193258, 6755869, 11317514, 3536186, 2448769, 6345647, -46347274, 17845044, 22709701, -438680, -14335177, 9198791, -8732116, 5173739}; - -int tf_real[1024] = {1048576, 1048556, 1048497, 1048398, 1048260, 1048082, 1047865, 1047608, 1047312, 1046977, 1046602, 1046188, 1045734, 1045241, 1044709, 1044137, 1043526, 1042876, 1042186, 1041458, 1040690, 1039883, 1039036, 1038151, 1037226, 1036263, 1035260, 1034218, 1033138, 1032019, 1030860, 1029663, 1028427, 1027153, 1025840, 1024488, 1023097, 1021668, 1020201, 1018695, 1017151, 1015569, 1013948, 1012289, 1010592, 1008857, 1007084, 1005273, 1003424, 1001538, 999613, 997651, 995652, 993615, 991541, 989429, 987280, 985094, 982871, 980610, 978313, 975979, 973609, 971201, 968757, 966277, 963760, 961207, 958618, 955993, 953331, 950634, 947901, 945132, 942328, 939488, 936613, 933703, 930757, 927777, 924761, 921711, 918626, 915506, 912352, 909163, 905941, 902684, 899393, 896068, 892710, 889318, 885893, 882434, 878942, 875417, 871859, 868268, 864644, 860988, 857299, 853578, 849825, 846040, 842224, 838375, 834495, 830583, 826641, 822667, 818662, 814626, 810560, 806463, 802336, 798178, 793991, 789773, 785526, 781249, 776943, 772608, 768243, 763850, 759428, 754977, 750498, 745990, 741455, 736891, 732300, 727681, 723035, 718362, 713661, 708934, 704180, 699400, 694593, 689760, 684901, 680016, 675106, 670170, 665209, 660223, 655212, 650177, 645117, 640032, 634924, 629792, 624635, 619456, 614253, 609027, 603778, 598506, 593212, 587896, 582557, 577197, 571814, 566410, 560985, 555539, 550072, 544584, 539075, 533547, 527998, 522429, 516841, 511233, 505606, 499960, 494295, 488611, 482909, 477189, 471451, 465695, 459922, 454131, 448324, 442499, 436658, 430800, 424926, 419036, 413130, 407209, 401272, 395320, 389354, 383373, 377377, 371367, 365343, 359305, 353254, 347190, 341112, 335022, 328919, 322803, 316676, 310536, 304385, 298222, 292049, 285864, 279668, 273462, 267246, 261019, 254783, 248537, 242281, 236017, 229744, 223462, 217172, 210873, 204567, 198252, 191931, 185602, 179266, 172923, 166574, 160219, 153858, 147490, 141118, 134740, 128356, 121968, 115576, 109179, 102778, 96373, 89965, 83553, 77138, 70720, 64299, 57876, 51451, 45024, 38595, 32164, 25733, 19300, 12867, 6433, 0, -6433, -12867, -19300, -25733, -32164, -38595, -45024, -51451, -57876, -64299, -70720, -77138, -83553, -89965, -96373, -102778, -109179, -115576, -121968, -128356, -134740, -141118, -147490, -153858, -160219, -166574, -172923, -179266, -185602, -191931, -198252, -204567, -210873, -217172, -223462, -229744, -236017, -242281, -248537, -254783, -261019, -267246, -273462, -279668, -285864, -292049, -298222, -304385, -310536, -316676, -322803, -328919, -335022, -341112, -347190, -353254, -359305, -365343, -371367, -377377, -383373, -389354, -395320, -401272, -407209, -413130, -419036, -424926, -430800, -436658, -442499, -448324, -454131, -459922, -465695, -471451, -477189, -482909, -488611, -494295, -499960, -505606, -511233, -516841, -522429, -527998, -533547, -539075, -544584, -550072, -555539, -560985, -566410, -571814, -577197, -582557, -587896, -593212, -598506, -603778, -609027, -614253, -619456, -624635, -629792, -634924, -640032, -645117, -650177, -655212, -660223, -665209, -670170, -675106, -680016, -684901, -689760, -694593, -699400, -704180, -708934, -713661, -718362, -723035, -727681, -732300, -736891, -741455, -745990, -750498, -754977, -759428, -763850, -768243, -772608, -776943, -781249, -785526, -789773, -793991, -798178, -802336, -806463, -810560, -814626, -818662, -822667, -826641, -830583, -834495, -838375, -842224, -846040, -849825, -853578, -857299, -860988, -864644, -868268, -871859, -875417, -878942, -882434, -885893, -889318, -892710, -896068, -899393, -902684, -905941, -909163, -912352, -915506, -918626, -921711, -924761, -927777, -930757, -933703, -936613, -939488, -942328, -945132, -947901, -950634, -953331, -955993, -958618, -961207, -963760, -966277, -968757, -971201, -973609, -975979, -978313, -980610, -982871, -985094, -987280, -989429, -991541, -993615, -995652, -997651, -999613, -1001538, -1003424, -1005273, -1007084, -1008857, -1010592, -1012289, -1013948, -1015569, -1017151, -1018695, -1020201, -1021668, -1023097, -1024488, -1025840, -1027153, -1028427, -1029663, -1030860, -1032019, -1033138, -1034218, -1035260, -1036263, -1037226, -1038151, -1039036, -1039883, -1040690, -1041458, -1042186, -1042876, -1043526, -1044137, -1044709, -1045241, -1045734, -1046188, -1046602, -1046977, -1047312, -1047608, -1047865, -1048082, -1048260, -1048398, -1048497, -1048556, -1048576, -1048556, -1048497, -1048398, -1048260, -1048082, -1047865, -1047608, -1047312, -1046977, -1046602, -1046188, -1045734, -1045241, -1044709, -1044137, -1043526, -1042876, -1042186, -1041458, -1040690, -1039883, -1039036, -1038151, -1037226, -1036263, -1035260, -1034218, -1033138, -1032019, -1030860, -1029663, -1028427, -1027153, -1025840, -1024488, -1023097, -1021668, -1020201, -1018695, -1017151, -1015569, -1013948, -1012289, -1010592, -1008857, -1007084, -1005273, -1003424, -1001538, -999613, -997651, -995652, -993615, -991541, -989429, -987280, -985094, -982871, -980610, -978313, -975979, -973609, -971201, -968757, -966277, -963760, -961207, -958618, -955993, -953331, -950634, -947901, -945132, -942328, -939488, -936613, -933703, -930757, -927777, -924761, -921711, -918626, -915506, -912352, -909163, -905941, -902684, -899393, -896068, -892710, -889318, -885893, -882434, -878942, -875417, -871859, -868268, -864644, -860988, -857299, -853578, -849825, -846040, -842224, -838375, -834495, -830583, -826641, -822667, -818662, -814626, -810560, -806463, -802336, -798178, -793991, -789773, -785526, -781249, -776943, -772608, -768243, -763850, -759428, -754977, -750498, -745990, -741455, -736891, -732300, -727681, -723035, -718362, -713661, -708934, -704180, -699400, -694593, -689760, -684901, -680016, -675106, -670170, -665209, -660223, -655212, -650177, -645117, -640032, -634924, -629792, -624635, -619456, -614253, -609027, -603778, -598506, -593212, -587896, -582557, -577197, -571814, -566410, -560985, -555539, -550072, -544584, -539075, -533547, -527998, -522429, -516841, -511233, -505606, -499960, -494295, -488611, -482909, -477189, -471451, -465695, -459922, -454131, -448324, -442499, -436658, -430800, -424926, -419036, -413130, -407209, -401272, -395320, -389354, -383373, -377377, -371367, -365343, -359305, -353254, -347190, -341112, -335022, -328919, -322803, -316676, -310536, -304385, -298222, -292049, -285864, -279668, -273462, -267246, -261019, -254783, -248537, -242281, -236017, -229744, -223462, -217172, -210873, -204567, -198252, -191931, -185602, -179266, -172923, -166574, -160219, -153858, -147490, -141118, -134740, -128356, -121968, -115576, -109179, -102778, -96373, -89965, -83553, -77138, -70720, -64299, -57876, -51451, -45024, -38595, -32164, -25733, -19300, -12867, -6433, 0, 6433, 12867, 19300, 25733, 32164, 38595, 45024, 51451, 57876, 64299, 70720, 77138, 83553, 89965, 96373, 102778, 109179, 115576, 121968, 128356, 134740, 141118, 147490, 153858, 160219, 166574, 172923, 179266, 185602, 191931, 198252, 204567, 210873, 217172, 223462, 229744, 236017, 242281, 248537, 254783, 261019, 267246, 273462, 279668, 285864, 292049, 298222, 304385, 310536, 316676, 322803, 328919, 335022, 341112, 347190, 353254, 359305, 365343, 371367, 377377, 383373, 389354, 395320, 401272, 407209, 413130, 419036, 424926, 430800, 436658, 442499, 448324, 454131, 459922, 465695, 471451, 477189, 482909, 488611, 494295, 499960, 505606, 511233, 516841, 522429, 527998, 533547, 539075, 544584, 550072, 555539, 560985, 566410, 571814, 577197, 582557, 587896, 593212, 598506, 603778, 609027, 614253, 619456, 624635, 629792, 634924, 640032, 645117, 650177, 655212, 660223, 665209, 670170, 675106, 680016, 684901, 689760, 694593, 699400, 704180, 708934, 713661, 718362, 723035, 727681, 732300, 736891, 741455, 745990, 750498, 754977, 759428, 763850, 768243, 772608, 776943, 781249, 785526, 789773, 793991, 798178, 802336, 806463, 810560, 814626, 818662, 822667, 826641, 830583, 834495, 838375, 842224, 846040, 849825, 853578, 857299, 860988, 864644, 868268, 871859, 875417, 878942, 882434, 885893, 889318, 892710, 896068, 899393, 902684, 905941, 909163, 912352, 915506, 918626, 921711, 924761, 927777, 930757, 933703, 936613, 939488, 942328, 945132, 947901, 950634, 953331, 955993, 958618, 961207, 963760, 966277, 968757, 971201, 973609, 975979, 978313, 980610, 982871, 985094, 987280, 989429, 991541, 993615, 995652, 997651, 999613, 1001538, 1003424, 1005273, 1007084, 1008857, 1010592, 1012289, 1013948, 1015569, 1017151, 1018695, 1020201, 1021668, 1023097, 1024488, 1025840, 1027153, 1028427, 1029663, 1030860, 1032019, 1033138, 1034218, 1035260, 1036263, 1037226, 1038151, 1039036, 1039883, 1040690, 1041458, 1042186, 1042876, 1043526, 1044137, 1044709, 1045241, 1045734, 1046188, 1046602, 1046977, 1047312, 1047608, 1047865, 1048082, 1048260, 1048398, 1048497, 1048556}; - -int tf_imag[1024] = {0, -6433, -12867, -19300, -25733, -32164, -38595, -45024, -51451, -57876, -64299, -70720, -77138, -83553, -89965, -96373, -102778, -109179, -115576, -121968, -128356, -134740, -141118, -147490, -153858, -160219, -166574, -172923, -179266, -185602, -191931, -198252, -204567, -210873, -217172, -223462, -229744, -236017, -242281, -248537, -254783, -261019, -267246, -273462, -279668, -285864, -292049, -298222, -304385, -310536, -316676, -322803, -328919, -335022, -341112, -347190, -353254, -359305, -365343, -371367, -377377, -383373, -389354, -395320, -401272, -407209, -413130, -419036, -424926, -430800, -436658, -442499, -448324, -454131, -459922, -465695, -471451, -477189, -482909, -488611, -494295, -499960, -505606, -511233, -516841, -522429, -527998, -533547, -539075, -544584, -550072, -555539, -560985, -566410, -571814, -577197, -582557, -587896, -593212, -598506, -603778, -609027, -614253, -619456, -624635, -629792, -634924, -640032, -645117, -650177, -655212, -660223, -665209, -670170, -675106, -680016, -684901, -689760, -694593, -699400, -704180, -708934, -713661, -718362, -723035, -727681, -732300, -736891, -741455, -745990, -750498, -754977, -759428, -763850, -768243, -772608, -776943, -781249, -785526, -789773, -793991, -798178, -802336, -806463, -810560, -814626, -818662, -822667, -826641, -830583, -834495, -838375, -842224, -846040, -849825, -853578, -857299, -860988, -864644, -868268, -871859, -875417, -878942, -882434, -885893, -889318, -892710, -896068, -899393, -902684, -905941, -909163, -912352, -915506, -918626, -921711, -924761, -927777, -930757, -933703, -936613, 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689760, 694593, 699400, 704180, 708934, 713661, 718362, 723035, 727681, 732300, 736891, 741455, 745990, 750498, 754977, 759428, 763850, 768243, 772608, 776943, 781249, 785526, 789773, 793991, 798178, 802336, 806463, 810560, 814626, 818662, 822667, 826641, 830583, 834495, 838375, 842224, 846040, 849825, 853578, 857299, 860988, 864644, 868268, 871859, 875417, 878942, 882434, 885893, 889318, 892710, 896068, 899393, 902684, 905941, 909163, 912352, 915506, 918626, 921711, 924761, 927777, 930757, 933703, 936613, 939488, 942328, 945132, 947901, 950634, 953331, 955993, 958618, 961207, 963760, 966277, 968757, 971201, 973609, 975979, 978313, 980610, 982871, 985094, 987280, 989429, 991541, 993615, 995652, 997651, 999613, 1001538, 1003424, 1005273, 1007084, 1008857, 1010592, 1012289, 1013948, 1015569, 1017151, 1018695, 1020201, 1021668, 1023097, 1024488, 1025840, 1027153, 1028427, 1029663, 1030860, 1032019, 1033138, 1034218, 1035260, 1036263, 1037226, 1038151, 1039036, 1039883, 1040690, 1041458, 1042186, 1042876, 1043526, 1044137, 1044709, 1045241, 1045734, 1046188, 1046602, 1046977, 1047312, 1047608, 1047865, 1048082, 1048260, 1048398, 1048497, 1048556, 1048576, 1048556, 1048497, 1048398, 1048260, 1048082, 1047865, 1047608, 1047312, 1046977, 1046602, 1046188, 1045734, 1045241, 1044709, 1044137, 1043526, 1042876, 1042186, 1041458, 1040690, 1039883, 1039036, 1038151, 1037226, 1036263, 1035260, 1034218, 1033138, 1032019, 1030860, 1029663, 1028427, 1027153, 1025840, 1024488, 1023097, 1021668, 1020201, 1018695, 1017151, 1015569, 1013948, 1012289, 1010592, 1008857, 1007084, 1005273, 1003424, 1001538, 999613, 997651, 995652, 993615, 991541, 989429, 987280, 985094, 982871, 980610, 978313, 975979, 973609, 971201, 968757, 966277, 963760, 961207, 958618, 955993, 953331, 950634, 947901, 945132, 942328, 939488, 936613, 933703, 930757, 927777, 924761, 921711, 918626, 915506, 912352, 909163, 905941, 902684, 899393, 896068, 892710, 889318, 885893, 882434, 878942, 875417, 871859, 868268, 864644, 860988, 857299, 853578, 849825, 846040, 842224, 838375, 834495, 830583, 826641, 822667, 818662, 814626, 810560, 806463, 802336, 798178, 793991, 789773, 785526, 781249, 776943, 772608, 768243, 763850, 759428, 754977, 750498, 745990, 741455, 736891, 732300, 727681, 723035, 718362, 713661, 708934, 704180, 699400, 694593, 689760, 684901, 680016, 675106, 670170, 665209, 660223, 655212, 650177, 645117, 640032, 634924, 629792, 624635, 619456, 614253, 609027, 603778, 598506, 593212, 587896, 582557, 577197, 571814, 566410, 560985, 555539, 550072, 544584, 539075, 533547, 527998, 522429, 516841, 511233, 505606, 499960, 494295, 488611, 482909, 477189, 471451, 465695, 459922, 454131, 448324, 442499, 436658, 430800, 424926, 419036, 413130, 407209, 401272, 395320, 389354, 383373, 377377, 371367, 365343, 359305, 353254, 347190, 341112, 335022, 328919, 322803, 316676, 310536, 304385, 298222, 292049, 285864, 279668, 273462, 267246, 261019, 254783, 248537, 242281, 236017, 229744, 223462, 217172, 210873, 204567, 198252, 191931, 185602, 179266, 172923, 166574, 160219, 153858, 147490, 141118, 134740, 128356, 121968, 115576, 109179, 102778, 96373, 89965, 83553, 77138, 70720, 64299, 57876, 51451, 45024, 38595, 32164, 25733, 19300, 12867, 6433}; - diff --git a/benchmarks/vec-fft/vec-fft_main.c b/benchmarks/vec-fft/vec-fft_main.c deleted file mode 100644 index b186205..0000000 --- a/benchmarks/vec-fft/vec-fft_main.c +++ /dev/null @@ -1,302 +0,0 @@ -// See LICENSE for license details. - -// ************************************************************************* -// multiply filter bencmark -// ------------------------------------------------------------------------- -// -// This benchmark tests the software multiply implemenation. The -// input data (and reference data) should be generated using the -// multiply_gendata.pl perl script and dumped to a file named -// dataset1.h You should not change anything except the -// HOST_DEBUG and VERIFY macros for your timing run. - -#include "vec-fft.h" - -//-------------------------------------------------------------------------- -// Macros - -// Set HOST_DEBUG to 1 if you are going to compile this for a host -// machine (ie Athena/Linux) for debug purposes and set HOST_DEBUG -// to 0 if you are compiling with the smips-gcc toolchain. - -#ifndef HOST_DEBUG -#define HOST_DEBUG 0 -#endif - -// Set PREALLOCATE to 1 if you want to preallocate the benchmark -// function before starting stats. If you have instruction/data -// caches and you don't want to count the overhead of misses, then -// you will need to use preallocation. - -#ifndef PREALLOCATE -#define PREALLOCATE 0 -#endif - -// Set VERIFY to 1 if you want the program to check that the sort -// function returns the right answer. When you are doing your -// benchmarking you should set this to 0 so that the verification -// is not included in your timing. - -#ifndef VERIFY -#define VERIFY 1 -#endif - -// Set SET_STATS to 1 if you want to carve out the piece that actually -// does the computation. - -#ifndef SET_STATS -#define SET_STATS 0 -#endif - -// Set MINIMAL to 1 if you want to run the core FFT kernel without -// any instrumentation or warm-up. -#ifndef MINIMAL -#define MINIMAL 1 -#endif - -//-------------------------------------------------------------------------- -// Platform Specific Includes - -#if HOST_DEBUG - #include - #include -#else -void printstr(const char*); -void exit(); -#endif - - -//-------------------------------------------------------------------------- -// Input/Reference Data - -#include "fft_const.h" - -//-------------------------------------------------------------------------- -// Helper functions - -#if !MINIMAL - -void setup_input(int n, fftval_t in_real[], fftval_t in_imag[]) -{ - int i; - for(i=0; i < n; i++) { - in_real[i] = input_data_real[i]; - in_imag[i] = input_data_imag[i]; - } -} -void setup_warm_tf(int n, fftval_t in_real[], fftval_t in_imag[]) -{ - int i; - for(i=0; i < n; i++) { - in_real[i] = tf_real[i]; - in_imag[i] = tf_imag[i]; - } -} - -fftval_t calculate_error( int n, const fftval_t test_real[], const fftval_t test_imag[]) -{ - fftval_t current_max = 0; - printf("idx, real expected, real observed, imag expected, imag observed %d\n", 0); - -#if defined(FFT_FIXED) - for(int i = 0; i < n; i++) - { - const double scale = 1 << FIX_PT; - const double real_diff = (test_real[i] - output_data_real[i])/scale; - const double imag_diff = (test_imag[i] - output_data_imag[i])/scale; - - const double i_sq_error = real_diff*real_diff + imag_diff*imag_diff; - if(i_sq_error > current_max) { - printf("i = %d, current error: %d\n", i, (long)current_max); - current_max = i_sq_error; - } - } -#elif defined(FFT_FLOATING) - fftval_t real_expect = 0.0; - fftval_t imag_expect = 0.0; - for(int i = 0; i < n; i++) - { - /* TODO: Fix error caculation for half precision */ - const fftval_t real_diff = (test_real[i] - output_data_real[i]); - const fftval_t imag_diff = (test_imag[i] - output_data_imag[i]); - fftval_t i_sq_error = real_diff*real_diff + imag_diff*imag_diff; - -#if 0 - long tr = (long)(test_real[i] * 1000000000); - long ti = (long)(test_imag[i] * 1000000000); - long er = (long)(output_data_real[i] * 1000000000); - long ei = (long)(output_data_imag[i] * 1000000000); - - printf("i = %d, expected (%d,%d) and got (%d,%d), diff (%d,%d)\n", - i, - er, ei, - tr, ti, - er-tr, ei-ti); -#endif - -#if 1 - fftbit_t tr, ti, er, ei; -#ifdef FP_HALF - tr = test_real[i]; - ti = test_imag[i]; - er = output_data_real[i]; - ei = output_data_imag[i]; -#else - union bits { - fftval_t v; - fftbit_t u; - } bits; - bits.v = test_real[i]; tr = bits.u; - bits.v = test_imag[i]; ti = bits.u; - bits.v = output_data_real[i]; er = bits.u; - bits.v = output_data_imag[i]; ei = bits.u; -#endif - printf("%d: %d %d %d %d\n", i, er, tr, ei, ti); - // printf("%4d\t" FFT_PRI "\t" FFT_PRI "\t" FFT_PRI "\t" FFT_PRI "\n", - // i, er, tr, ei, ti); -#endif - -#if 0 - if(i_sq_error > current_max) { - printf("i = %d, max error (ppb): %ld\n", i, (long)(current_max * 1000000000)); - current_max = i_sq_error; - real_expect = output_data_real[i]; - imag_expect = output_data_imag[i]; - } -#endif - } -/* - printf("real expected: %d\n", (long)(real_expect)); - printf("imag expected: %d\n", (long)(imag_expect)); -*/ -#endif - - return current_max; -} - -void finishTest( double max_sq_error, long long num_cycles, long long num_retired) -{ - int passed = max_sq_error < 10e-8; - - if( passed ) printstr("*** PASSED ***"); - else printstr("*** FAILED ***"); - - printf(" (num_cycles = %ld, num_inst_retired = %ld)\n", num_cycles, num_retired); - - passed = passed ? 1 : 2; // if it passed, return 1 - - exit(); -} - -void setStats( int enable ) -{ -#if ( !HOST_DEBUG && SET_STATS ) - //asm( "mtpcr %0, cr10" : : "r" (enable) ); -#endif -} - -long long getCycles() -{ - long long cycles = 1337; -#if ( !HOST_DEBUG && SET_STATS ) - __asm__ __volatile__( "rdcycle %0" : "=r" (cycles) ); -#endif - return cycles; -} - -long long getInstRetired() -{ - long long inst_retired = 1338; -#if ( !HOST_DEBUG && SET_STATS ) - __asm__ __volatile__( "rdinstret %0" : "=r" (inst_retired) ); -#endif - return inst_retired; -} - -#endif /* !MINIMAL */ - -//-------------------------------------------------------------------------- -// Main -#define HWACHA_RADIX 2 - -#ifdef DATA_IN_UNPERMUTED -void permute(fftval_t workspace_real[], fftval_t workspace_imag[]) -{ - const int logradix = log2down(HWACHA_RADIX); - const int term_mask = HWACHA_RADIX-1; - const int num_term = log2down(FFT_SIZE)/logradix; - for(int i = 0; i < FFT_SIZE; i++) - { - // Get permuted address - int i_left = i; - int permuted = 0; - for(int cur_fft_size=HWACHA_RADIX; cur_fft_size <= FFT_SIZE; cur_fft_size = cur_fft_size << logradix) - { - permuted = (permuted << logradix) | (i_left & term_mask); - i_left = i_left >> logradix; - } - // If addresses are different and i < permuted (so we only do permutation once) - if(i < permuted) - { - fftval_t t = workspace_real[i]; - fftval_t u = workspace_imag[i]; - workspace_real[i] = workspace_real[permuted]; - workspace_imag[i] = workspace_imag[permuted]; - workspace_real[permuted] = t; - workspace_imag[permuted] = u; - } - } -} -#endif /* DATA_IN_UNPERMUTED */ - -#if MINIMAL - -int main(void) -{ -#ifdef DATA_IN_UNPERMUTED - permute(input_data_real, input_data_imag); -#endif - fft(input_data_real, input_data_imag, tf_real, tf_imag); -// calculate_error(FFT_SIZE, input_data_real, input_data_imag); - exit(); -} - -#else /* !MINIMAL */ - -int main(void) -{ - static fftval_t workspace_real[FFT_SIZE]; - static fftval_t workspace_imag[FFT_SIZE]; - static fftval_t warm_tf_real[FFT_SIZE]; - static fftval_t warm_tf_imag[FFT_SIZE]; - setup_input(FFT_SIZE, workspace_real, workspace_imag); - setup_warm_tf(FFT_SIZE, warm_tf_real, warm_tf_imag); - -#if PREALLOCATE - fft(workspace_real, workspace_imag, warm_tf_real, warm_tf_imag); - setup_input(FFT_SIZE, workspace_real, workspace_imag); -#endif - - long long start_cycles, start_retired, stop_cycles, stop_retired; - start_cycles = getCycles(); - start_retired = getInstRetired(); - -#ifdef DATA_IN_UNPERMUTED - permute(workspace_real, workspace_imag); -#endif - setStats(1); - fft(workspace_real, workspace_imag, warm_tf_real, warm_tf_imag); - setStats(0); - - stop_cycles = getCycles(); - stop_retired = getInstRetired(); - long long num_cycles = stop_cycles - start_cycles; - long long num_retired = stop_retired - start_retired; - - const double max_sq_error = calculate_error(FFT_SIZE, workspace_real, workspace_imag); - - // Check the results - finishTest(max_sq_error, num_cycles, num_retired); -} - -#endif /* MINIMAL */ diff --git a/benchmarks/vec-fft/vec-vfft.S b/benchmarks/vec-fft/vec-vfft.S deleted file mode 100644 index 05706af..0000000 --- a/benchmarks/vec-fft/vec-vfft.S +++ /dev/null @@ -1,245 +0,0 @@ -# See LICENSE for license details. - - .text - .align 2 - -#include "fft_const.h" - -#if defined(FFT_FIXED) - #define PTR_SHIFT 2 - #define PTR_SIZE 4 - - #define DATA_LOAD lw - #define DATA_STORE sw - - #define FFT_MUL mul - #define FFT_ADD add - #define FFT_SUB sub - - #define REG0 x3 - #define REG1 x4 - #define REG2 x5 - #define REG3 x6 - #define REG4 x7 - #define REG5 x8 -#elif defined(FFT_FLOATING) - #if defined(FP_HALF) - #define PTR_SHIFT 1 - #define PTR_SIZE 2 - - #define DATA_LOAD flh - #define DATA_STORE fsh - - #define FFT_MUL fmul.h - #define FFT_ADD fadd.h - #define FFT_SUB fsub.h - #elif defined(FP_SINGLE) - #define PTR_SHIFT 2 - #define PTR_SIZE 4 - - #define DATA_LOAD flw - #define DATA_STORE fsw - - #define FFT_MUL fmul.s - #define FFT_ADD fadd.s - #define FFT_SUB fsub.s - #elif defined(FP_DOUBLE) - #define PTR_SHIFT 3 - #define PTR_SIZE 8 - - #define DATA_LOAD fld - #define DATA_STORE fsd - - #define FFT_MUL fmul.d - #define FFT_ADD fadd.d - #define FFT_SUB fsub.d - #endif - - #define REG0 f0 - #define REG1 f1 - #define REG2 f2 - #define REG3 f3 - #define REG4 f4 - #define REG5 f5 -#else - #error FFT_FIXED or FFT_FLOATING not defined -#endif - - .globl vf_test -vf_test: - utidx x2 - add x1, x1, x2 - add x1, x1, x1 - stop - - .globl vf_fft_init -vf_fft_init: -# IN: -# x1: lane start (utidx=0 actually has this pos due to stripmining) -# x2: bit mask to select FFT block from op idx -# x3: bit mask to select operand in FFT block from op idx -# x4: necessary shift to adjust TF appropriately ( REMOVED ) -# x5: half the current FFT size (add to get the second op) -# OUT: -# x1: Has the first operand pos = (opid & i_x2) << 1 + (opid & i_x3) -# x2: Has the second operand pos = o_x1 + i_x5 -# x3: Has the twiddle factor pos = (opid & i_x3) << i_x4 - utidx x6 - add x6, x1, x6 # x6 <= opid - and x2, x2, x6 # x2 <= opid & i_x2 - and x3, x3, x6 # x3 <= opid & i_x3 - slli x2, x2, 1 # x2 <= (opid & i_x2) << 1 - - add x1, x2, x3 # x1 is now the proper result - add x2, x1, x5 # x2 is now the proper result - sll x3, x3, x4 - - stop - - .globl vf_fft_scale -vf_fft_scale: -# IN: -# x1: Has the first operand pos (reused) -# x2: Has the second operand pos (reused) -# x3: Has the twiddle factor pos (reused) -# x4: Has the tf real ptr -# x5: Has the tf imag ptr -# x6: Has the workspace real ptr -# x7: Has the workspace imag ptr -# x8: Has the fixed point shift ( REMOVED ) -# OUT: -# x1: Has the first operand offset = i_x1 << 3 -# x2: Has the second operand offset = i_x2 << 3 -# x3: Has the scale factor real -# x4: Has the scale factor imag - # Convert positions into actual memory offsets from table start - slli x1, x1, PTR_SHIFT # x1 <= i_x1 << 3 (proper result) - slli x2, x2, PTR_SHIFT # x2 <= i_x2 << 3 (proper result) - slli x3, x3, PTR_SHIFT # x3 <= i_x3 << 3 (tf offset) - - # Compute memory locations - add x4, x4, x3 # x4 <= load address for tf real - add x5, x5, x3 # x5 <= load address for tf imag - add x6, x6, x2 # x6 <= load address for op2 real - add x7, x7, x2 # x7 <= load address for op2 imag - - # Actually read memory - DATA_LOAD REG1, 0(x4) # tf real (a) - DATA_LOAD REG2, 0(x5) # tf imag (bi) - DATA_LOAD REG3, 0(x6) # op2 real (c) - DATA_LOAD REG4, 0(x7) # op2 imag (di) - - # Do the math using 3 multiplies - FFT_ADD REG0, REG1, REG2 # REG0 <= a + b - FFT_SUB REG2, REG2, REG1 # REG2 <= b - a - FFT_MUL REG0, REG0, REG4 # REG0 <= (a+b)d -#ifdef FFT_FIXED - sra REG0, REG0, REG5 # DO NOT SHIFT FOR FLOATING -#endif - FFT_MUL REG2, REG2, REG3 # REG2 <= (b-a)c -#ifdef FFT_FIXED - sra REG2, REG2, REG5 # DO NOT SHIFT FOR FLOATING -#endif - FFT_ADD REG3, REG3, REG4 # REG3 <= c + d - FFT_MUL REG4, REG1, REG3 # REG4 <= a(c+d) -#ifdef FFT_FIXED - sra REG4, REG4, REG5 # DO NOT SHIFT FOR FLOATING -#endif - - # Prepare final result - FFT_SUB REG0, REG4, REG0 # REG0 <= a(c+d) - (a+b)d (scale real) - FFT_ADD REG1, REG4, REG2 # REG1 <= a(c+d) + (b-a)c (scale imag) - - stop -/* - # Four multiply version - # Do the multiplications (a+bi)(c+di) needs ac ad bc bd - mul x3, x4, x6 # x3 <= ac - mul x4, x4, x7 # x4 <= adi - mul x6, x5, x6 # x6 <= bc - mul x5, x5, x7 # x5 <= bdi - sra x3, x3, x8 # These 4 shifts make sure the fixed pt properly aligned - sra x4, x4, x8 - sra x5, x5, x8 - sra x6, x6, x8 - - # Do the additions (ac - bd) and (bc + ad) - sub x3, x3, x5 # x3 <= ac - bd (proper result) - add x4, x4, x6 # x4 <= bc + ad (proper result) -*/ - - .globl vf_fft_exec -vf_fft_exec: -# IN: -# x1: Has the first operand offset (reused) -# x2: Has the second operand offset (reused) -# x3: Has the scale factor real (reused) -# x4: Has the scale factor imag (reused) -# x5: Has the workspace real ptr -# x6: Has the workspace imag ptr -# OUT: -# x1: Has the first operand offset (carry) -# x2: Has the second operand offset (carry) -# x5: Has the first result real -# x6: Has the first result imag -# x7: Has the second result real -# x8: Has the second result imag - # Compute first operand memory locations - add x5, x5, x1 # x5 <= load address for op1 real - add x6, x6, x1 # x6 <= load address for op1 imag - - #actually read memory - DATA_LOAD REG2, 0(x5) # op1 real - DATA_LOAD REG3, 0(x6) # op1 imag - - # Do the add/subs (res1=op1+scale), (res2=op1-scale) - FFT_SUB REG4, REG2, REG0 # res2 real - FFT_SUB REG5, REG3, REG1 # res2 imag - FFT_ADD REG2, REG2, REG0 # res1 real - FFT_ADD REG3, REG3, REG1 # res1 imag - - stop - - .globl vf_fft_store1 -vf_fft_store1: -# IN: -# x1: Has the first operand offset (reused) -# x2: Has the second operand offset (reused) -# x3: Has the workspace real ptr -# x4: Has the workspace imag ptr -# x5: Has the first result real (reused) -# x6: Has the first result imag (reused) -# x7: Has the second result real (reused) -# x8: Has the second result imag (reused) -# OUT: -# x2: Has the second operand offset (carry) -# x7: Has the second result real (carry) -# x8: Has the second result imag (carry) - # Compute first result memory locations - add x3, x3, x1 - add x4, x4, x1 - - # actually write memory - DATA_STORE REG2, 0(x3) - DATA_STORE REG3, 0(x4) - - stop - - .globl vf_fft_store2 -vf_fft_store2: -# IN: -# x2: Has the second operand offset -# x3: Has the workspace real ptr -# x4: Has the workspace imag ptr -# x7: Has the second result real -# x8: Has the second result imag -# OUT: (none) - # Compute second result memory locations - add x3, x3, x2 - add x4, x4, x2 - - # actually write memory - DATA_STORE REG4, 0(x3) - DATA_STORE REG5, 0(x4) - - stop diff --git a/benchmarks/vec-matmul/bmark.mk b/benchmarks/vec-matmul/bmark.mk deleted file mode 100644 index a503f7b..0000000 --- a/benchmarks/vec-matmul/bmark.mk +++ /dev/null @@ -1,30 +0,0 @@ -#======================================================================= -# UCB CS250 Makefile fragment for benchmarks -#----------------------------------------------------------------------- -# -# Each benchmark directory should have its own fragment which -# essentially lists what the source files are and how to link them -# into an riscv and/or host executable. All variables should include -# the benchmark name as a prefix so that they are unique. -# - -vec_matmul_c_src = \ - vec_matmul_main.c \ - -vec_matmul_riscv_src = \ - crt.S \ - vec_matmul_asm.S - -vec_matmul_c_objs = $(patsubst %.c, %.o, $(vec_matmul_c_src)) -vec_matmul_riscv_objs = $(patsubst %.S, %.o, $(vec_matmul_riscv_src)) - -vec_matmul_host_bin = vec-matmul.host -$(vec_matmul_host_bin) : $(vec_matmul_c_src) - $(HOST_COMP) $^ -o $(vec_matmul_host_bin) - -vec_matmul_riscv_bin = vec-matmul.riscv -$(vec_matmul_riscv_bin) : $(vec_matmul_c_objs) $(vec_matmul_riscv_objs) - $(RISCV_LINK) $(RISCV_LINK_SYSCALL) $(vec_matmul_c_objs) $(vec_matmul_riscv_objs) -o $(vec_matmul_riscv_bin) - -junk += $(vec_matmul_c_objs) $(vec_matmul_riscv_objs) \ - $(vec_matmul_host_bin) $(vec_matmul_riscv_bin) diff --git a/benchmarks/vec-matmul/dataset.h b/benchmarks/vec-matmul/dataset.h deleted file mode 100644 index 99fb974..0000000 --- a/benchmarks/vec-matmul/dataset.h +++ /dev/null @@ -1,635 +0,0 @@ -// See LICENSE for license details. - - -#define ARRAY_SIZE 4096 - - -#define DIM_SIZE 64 - -float input1_data[ARRAY_SIZE] = -{ - 0.37, 7.51, 5.09, 1.69, 6.75, 3.16, 1.19, 8.56, 5.26, 7.26, 5.60, 0.06, 8.39, 8.02, 3.54, 6.25, 8.66, 1.00, 1.05, 2.67, - 3.84, 2.83, 5.94, 6.97, 2.88, 6.12, 7.88, 3.40, 4.27, 8.45, 4.86, 5.13, 1.83, 2.53, 6.84, 5.46, 4.61, 5.93, 1.76, 0.74, - 2.41, 2.06, 3.04, 8.51, 8.13, 2.18, 8.23, 7.45, 8.41, 8.88, 1.77, 8.65, 5.11, 3.16, 5.85, 5.92, 1.63, 1.01, 7.74, 0.59, - 2.60, 3.15, 1.28, 8.16, 7.98, 2.38, 5.20, 8.83, 6.86, 2.17, 4.31, 4.50, 3.63, 2.00, 4.00, 6.50, 6.09, 2.86, 2.02, 8.45, - 2.60, 1.08, 5.54, 5.46, 3.51, 3.16, 4.10, 2.51, 3.31, 3.23, 5.26, 0.57, 8.88, 3.63, 3.12, 4.66, 5.04, 8.18, 6.99, 2.30, - 7.02, 5.39, 1.29, 0.31, 1.13, 8.48, 8.41, 7.20, 4.98, 3.89, 5.85, 8.58, 2.59, 0.18, 0.45, 0.78, 0.86, 3.98, 5.29, 5.54, - 3.44, 2.53, 7.28, 8.75, 7.38, 3.11, 4.06, 4.62, 8.70, 3.13, 7.29, 7.95, 4.84, 8.53, 6.32, 3.21, 5.12, 8.03, 0.20, 5.12, - 6.00, 3.81, 3.91, 1.43, 0.02, 0.76, 2.23, 0.45, 3.92, 7.14, 7.83, 4.38, 3.73, 3.33, 4.94, 4.67, 8.00, 6.15, 2.57, 2.38, - 4.50, 2.62, 8.08, 1.94, 6.59, 6.20, 2.26, 7.08, 5.01, 2.72, 4.76, 4.91, 2.90, 8.54, 2.59, 7.42, 2.75, 7.11, 6.61, 8.65, - 3.30, 6.51, 2.65, 8.79, 5.89, 6.75, 0.82, 3.41, 0.95, 0.93, 3.44, 5.87, 7.44, 7.57, 3.22, 1.34, 0.49, 1.26, 8.61, 3.09, - 4.81, 6.82, 4.70, 7.55, 5.34, 0.12, 1.56, 0.57, 1.09, 1.20, 6.83, 3.35, 8.57, 0.36, 1.17, 1.00, 7.64, 3.94, 2.30, 2.43, - 3.69, 5.66, 3.60, 4.95, 6.79, 5.08, 1.54, 0.17, 6.55, 4.52, 7.01, 0.39, 6.79, 0.73, 1.82, 7.69, 1.39, 6.85, 3.22, 8.50, - 8.31, 2.96, 4.47, 3.99, 4.66, 5.78, 2.49, 7.08, 1.03, 7.59, 8.17, 2.48, 2.14, 0.30, 7.07, 5.09, 3.22, 7.24, 7.38, 6.77, - 2.52, 0.77, 4.13, 4.10, 6.40, 4.14, 0.38, 2.28, 3.40, 4.58, 6.31, 7.75, 4.33, 6.68, 4.50, 6.39, 0.45, 3.35, 7.87, 8.52, - 8.94, 4.75, 6.50, 3.92, 2.10, 4.48, 6.29, 0.28, 3.14, 2.26, 3.16, 2.26, 5.17, 7.06, 6.75, 4.53, 7.42, 7.45, 1.53, 1.45, - 6.08, 0.29, 1.82, 1.29, 7.69, 0.81, 3.56, 0.97, 7.70, 0.96, 1.42, 0.05, 6.90, 1.84, 1.76, 5.18, 1.97, 4.74, 1.60, 2.16, - 6.30, 6.82, 6.37, 0.45, 0.76, 7.21, 8.05, 4.62, 3.36, 4.44, 0.13, 5.60, 0.75, 0.93, 7.16, 8.30, 5.79, 7.93, 7.52, 2.16, - 4.16, 1.03, 5.06, 4.77, 0.09, 8.98, 8.15, 3.49, 3.67, 0.95, 5.04, 8.44, 4.62, 3.69, 2.73, 1.82, 3.85, 5.53, 3.24, 4.70, - 6.17, 0.20, 1.67, 2.82, 0.97, 2.48, 3.49, 2.19, 4.38, 0.95, 6.30, 8.10, 6.94, 5.81, 0.73, 1.46, 3.67, 8.52, 0.27, 6.92, - 7.84, 1.03, 1.34, 0.56, 1.33, 7.55, 7.61, 3.90, 1.27, 1.90, 7.36, 7.40, 5.07, 3.28, 5.55, 4.47, 7.32, 8.26, 1.44, 3.88, - 7.24, 1.62, 4.91, 7.57, 4.13, 7.09, 7.86, 7.17, 7.26, 6.83, 0.94, 3.62, 2.29, 8.87, 1.23, 6.57, 5.27, 7.16, 3.74, 4.76, - 6.37, 4.99, 3.41, 6.91, 8.80, 2.13, 8.54, 2.07, 1.49, 4.56, 0.95, 6.35, 7.17, 1.26, 2.74, 7.17, 5.72, 5.05, 1.07, 0.08, - 4.79, 7.33, 0.34, 5.27, 6.67, 5.58, 6.91, 4.31, 0.52, 8.64, 7.07, 8.88, 7.54, 2.77, 0.61, 7.43, 8.98, 6.75, 1.55, 7.44, - 5.60, 1.40, 7.44, 0.39, 6.25, 0.73, 2.13, 6.74, 6.71, 2.40, 1.12, 6.59, 8.49, 3.83, 3.34, 2.89, 2.43, 4.89, 6.88, 6.78, - 8.25, 0.13, 0.01, 8.16, 8.97, 7.30, 5.05, 7.87, 8.76, 2.61, 4.59, 5.03, 8.74, 3.65, 5.22, 2.64, 2.26, 7.66, 1.16, 4.08, - 6.45, 0.78, 6.12, 1.64, 2.17, 3.03, 7.15, 5.78, 0.01, 2.88, 8.89, 5.83, 6.80, 8.64, 1.83, 1.28, 1.62, 2.70, 1.49, 6.86, - 8.78, 5.83, 5.04, 5.58, 3.81, 2.35, 5.10, 4.88, 4.44, 8.93, 6.72, 1.87, 3.36, 8.40, 5.99, 0.31, 4.81, 4.31, 8.19, 1.83, - 0.30, 1.93, 3.30, 8.04, 7.04, 6.13, 6.35, 6.20, 8.53, 3.48, 0.45, 0.91, 4.28, 3.60, 6.12, 2.97, 8.59, 4.25, 4.30, 6.54, - 6.43, 8.45, 4.77, 7.84, 0.70, 4.91, 8.18, 7.69, 1.29, 8.82, 2.16, 0.95, 3.29, 0.89, 0.49, 0.88, 3.96, 6.89, 2.84, 3.03, - 6.28, 6.98, 6.54, 2.92, 2.55, 4.83, 5.61, 5.36, 8.02, 0.68, 2.62, 4.47, 6.54, 4.05, 4.94, 1.22, 5.81, 7.55, 2.61, 6.91, - 1.47, 3.75, 4.43, 8.88, 1.05, 5.57, 7.74, 2.12, 2.55, 5.15, 8.23, 5.05, 1.76, 2.18, 7.05, 8.88, 6.56, 3.10, 3.88, 5.52, - 6.85, 1.59, 2.79, 3.01, 3.19, 2.79, 6.30, 0.42, 4.39, 4.54, 0.91, 3.54, 2.42, 2.83, 0.68, 3.12, 8.90, 5.41, 8.19, 3.47, - 0.83, 4.91, 2.50, 6.02, 3.17, 7.69, 7.78, 2.82, 0.91, 4.80, 5.12, 7.53, 3.34, 8.92, 4.16, 8.22, 1.64, 2.42, 1.44, 6.95, - 0.20, 7.70, 5.81, 0.16, 7.02, 8.21, 7.71, 1.24, 8.86, 6.46, 5.09, 6.48, 2.28, 7.08, 1.39, 1.77, 2.29, 4.03, 8.10, 0.05, - 2.94, 5.55, 2.78, 1.58, 1.44, 1.11, 7.56, 6.45, 4.96, 2.07, 0.74, 5.65, 2.92, 8.35, 0.93, 0.16, 8.71, 1.43, 1.60, 5.35, - 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1285.27, 1410.21, 1227.75, 1258.55, 1568.65, 1294.37, 1346.73, 1355.97, 1291.39, 1491.92, 1433.87, 1383.22, 1234.42, 1480.98, 1431.55, 1394.94, 1451.04, 1461.42, 1480.30, 1390.20, - 1451.88, 1559.52, 1316.89, 1396.52, 1385.16, 1549.24, 1376.21, 1352.67, 1490.72, 1377.56, 1324.12, 1288.39, 1486.11, 1401.94, 1597.30, 1393.09, 1393.10, 1527.19, 1346.17, 1403.61, - 1329.84, 1428.33, 1697.28, 1486.74, 1610.30, 1524.46, 1536.59, 1601.98, 1406.43, 1537.88, 1518.79, 1379.87, 1151.81, 1615.09, 1448.84, 1386.40, 1198.14, 1206.61, 1238.94, 1358.98, - 1104.33, 1060.02, 1132.03, 1218.76, 1148.86, 1139.73, 1011.63, 1011.10, 1253.39, 1145.71, 1046.80, 1098.42, 1133.10, 1332.54, 1114.50, 1108.41, 1095.69, 1186.49, 1088.61, 1177.96, - 1179.91, 1080.40, 1232.01, 1178.43, 1295.16, 1337.88, 1089.30, 1138.30, 982.34, 1238.16, 1193.96, 1128.41, 1226.30, 1110.66, 1201.22, 1026.73, 1099.94, 1082.45, 1286.87, 1182.08, - 1161.86, 1229.94, 1118.10, 1169.49, 1059.97, 1106.63, 1337.81, 1198.73, 1338.76, 1140.70, 1176.55, 1411.23, 1066.54, 1225.73, 1285.37, 1105.53, 995.55, 1251.52, 1296.70, 1183.81, - 1336.82, 1359.41, 1531.23, 1506.89, 1277.25, 1341.98, 1207.09, 1441.27, 1245.61, 1279.99, 1171.33, 1203.39, 1552.78, 1221.36, 1278.65, 1229.00, 1212.91, 1567.53, 1327.70, 1240.24, - 1221.25, 1366.21, 1299.23, 1329.50, 1364.06, 1221.40, 1345.24, 1276.10, 1358.50, 1499.46, 1370.30, 1533.58, 1307.25, 1541.06, 1373.60, 1256.80, 1411.07, 1472.58, 1381.63, 1209.79, - 1385.44, 1228.53, 1579.26, 1332.83, 1430.57, 1425.45, 1391.60, 1288.74, 1244.24, 1275.17, 1516.60, 1474.56, 1448.48, 1489.99, 1368.60, 1592.46, 1335.75, 1411.22, 1432.70, 1267.68, - 1041.35, 1491.54, 1498.69, 1323.89, 1179.47, 1288.17, 1343.09, 1495.42, 1190.80, 1208.26, 1233.67, 1266.03, 1009.92, 1189.92, 1079.33, 1226.48, 1415.04, 1174.65, 1095.22, 1124.00, - 1118.95, 1334.79, 1243.54, 1187.79, 1081.39, 1204.17, 1153.96, 1225.61, 1165.12, 1278.03, 1207.02, 1105.44, 1266.90, 1290.10, 1156.28, 1332.57, 1130.42, 1364.51, 1124.01, 1162.57, - 1257.70, 1224.27, 1163.35, 1089.64, 1331.68, 1111.06, 1321.76, 1210.18, 1203.34, 1320.04, 1119.50, 1162.15, 1211.72, 1226.56, 1418.76, 1345.12, 1364.04, 1344.66, 1322.72, 1369.63, - 1197.77, 1342.54, 1295.97, 1116.95, 1010.17, 1336.54, 1207.94, 1273.88, 1234.22, 1145.59, 1273.48, 1352.87, 1111.27, 1229.25, 1105.41, 1236.72, 1114.96, 1128.70, 1001.74, 1106.89, - 1306.04, 1147.72, 1139.74, 1197.38, 1101.79, 1346.01, 1193.67, 1053.84, 997.60, 1243.23, 1132.20, 1140.96, 1188.55, 1128.00, 1141.85, 1152.23, 1186.89, 1293.55, 1165.47, 1241.90, - 1114.40, 1382.10, 1174.74, 1128.36, 1206.13, 1252.88, 1163.47, 1058.72, 1157.54, 1136.36, 1452.71, 1189.00, 1158.47, 1286.42, 1087.34, 1117.48, 1059.71, 1200.30, 1363.05, 1194.97, - 1287.62, 1371.77, 1242.62, 1381.55, 1162.41, 1153.85, 1296.64, 1183.91, 1104.32, 1302.69, 1248.47, 1127.57, 1541.65, 1449.79, 1543.72, 1669.84, 1552.41, 1442.87, 1419.15, 1516.45, - 1365.70, 1418.19, 1283.35, 1397.02, 1636.63, 1330.73, 1354.17, 1396.58, 1343.54, 1676.34, 1545.03, 1346.49, 1205.89, 1582.05, 1492.58, 1339.30, 1505.07, 1445.89, 1521.83, 1438.11, - 1514.20, 1537.87, 1457.46, 1563.90, 1380.61, 1640.16, 1372.38, 1522.58, 1470.40, 1587.96, 1514.42, 1344.65, 1492.48, 1285.49, 1721.76, 1459.99, 1440.06, 1547.91, 1372.78, 1443.99, - 1427.05, 1452.09, 1730.53, 1504.18, 1661.41, 1506.44, 1466.96, 1729.20, 1424.56, 1526.45, 1623.14, 1377.34, 1328.57, 1535.54, 1486.59, 1426.21, 1251.77, 1271.32, 1385.16, 1513.24, - 1214.50, 1329.88, 1281.79, 1400.95, 1181.91, 1193.78, 1112.89, 1162.70, 1409.60, 1309.09, 1324.74, 1200.69, 1270.76, 1404.72, 1270.69, 1247.59, 1133.68, 1276.68, 1301.66, 1287.50, - 1245.47, 1231.10, 1338.69, 1224.15, 1459.25, 1460.39, 1298.97, 1267.27, 1198.90, 1420.61, 1242.62, 1373.64, 1278.89, 1310.16, 1265.24, 1162.40, 1356.80, 1323.82, 1486.75, 1340.86, - 1272.36, 1425.28, 1252.32, 1345.57, 1290.27, 1190.63, 1562.44, 1439.95, 1476.36, 1440.54, 1413.98, 1475.85, 1274.13, 1332.14, 1366.48, 1104.44, 1112.21, 1401.95, 1403.46, 1325.29, - 1319.27, 1331.63, 1332.49, 1472.21, 1325.58, 1311.89, 1312.22, 1480.80, 1108.58, 1245.66, 1143.69, 1163.06, 1536.72, 1239.62, 1193.78, 1265.51, 1140.02, 1461.12, 1311.68, 1260.50, - 1243.53, 1288.05, 1197.69, 1253.15, 1319.70, 1266.22, 1272.58, 1219.48, 1293.98, 1487.47, 1178.02, 1344.72, 1268.21, 1537.06, 1283.91, 1289.73, 1395.59, 1376.58, 1319.33, 1045.68, - 1310.65, 1386.68, 1532.68, 1377.28, 1279.59, 1366.86, 1403.80, 1200.92, 1189.43, 1248.40, 1591.06, 1355.88, 1377.70, 1451.58, 1480.72, 1472.42, 1246.27, 1399.85, 1400.35, 1235.28, - 1124.89, 1407.01, 1319.83, 1301.32, 1415.13, 1365.13, 1452.19, 1604.11, 1500.89, 1435.12, 1385.70, 1390.88, 1370.55, 1371.05, 1134.74, 1227.42, 1515.15, 1335.13, 1326.54, 1236.30, - 1336.05, 1528.68, 1271.89, 1289.61, 1315.37, 1554.50, 1310.00, 1258.95, 1371.55, 1340.63, 1338.41, 1482.49, 1431.91, 1526.41, 1323.51, 1506.38, 1300.72, 1450.18, 1375.10, 1555.41, - 1385.68, 1408.90, 1439.56, 1172.49, 1303.00, 1284.11, 1561.57, 1510.37, 1392.96, 1444.72, 1355.37, 1344.74, 1334.03, 1237.49, 1698.61, 1301.14, 1501.12, 1497.12, 1406.61, 1668.88, - 1271.92, 1409.82, 1568.31, 1247.27, 1268.28, 1506.07, 1487.85, 1331.96, 1308.11, 1153.87, 1349.43, 1394.82, 1370.40, 1305.67, 1238.26, 1244.13, 1212.34, 1214.01, 1057.37, 1222.82, - 1462.63, 1146.31, 1176.44, 1233.37, 1219.87, 1417.39, 1256.23, 1141.71, 1104.27, 1342.60, 1107.36, 1166.71, 1269.03, 1296.78, 1394.75, 1203.71, 1303.12, 1292.80, 1349.62, 1268.20, - 1282.37, 1365.87, 1257.10, 1301.37, 1223.24, 1357.85, 1295.40, 1080.32, 1259.42, 1103.25, 1505.06, 1378.76, 1259.55, 1407.08, 1277.81, 1274.20, 1239.76, 1259.26, 1419.32, 1290.93, - 1461.62, 1392.77, 1208.72, 1487.44, 1233.27, 1167.01, 1408.25, 1166.39, 1115.86, 1476.19, 1408.85, 1255.06, 1318.64, 1417.57, 1440.11, 1502.85, 1377.80, 1417.09, 1331.16, 1321.85, - 1168.14, 1336.71, 1255.18, 1308.91, 1564.34, 1217.88, 1191.89, 1256.18, 1238.63, 1484.72, 1428.50, 1188.80, 1197.03, 1352.54, 1233.73, 1210.42, 1334.10, 1343.73, 1344.27, 1247.66, - 1422.34, 1501.63, 1308.65, 1456.09, 1333.68, 1538.77, 1309.99, 1554.85, 1368.45, 1371.48, 1286.55, 1192.83, 1372.63, 1244.44, 1486.45, 1447.41, 1312.79, 1416.11, 1354.57, 1335.71, - 1289.82, 1212.67, 1601.19, 1401.01, 1527.72, 1468.40, 1434.39, 1541.73, 1275.53, 1436.32, 1532.78, 1246.52, 1183.33, 1431.59, 1398.14, 1389.18 -}; - diff --git a/benchmarks/vec-matmul/dataset_test.h b/benchmarks/vec-matmul/dataset_test.h deleted file mode 100644 index d9244de..0000000 --- a/benchmarks/vec-matmul/dataset_test.h +++ /dev/null @@ -1,41 +0,0 @@ -// See LICENSE for license details. - - -#define ARRAY_SIZE 4 - - -#define DIM_SIZE 2 - -#if 1 -float input1_data[ARRAY_SIZE] = -{ - 0.37, 7.51, 5.09, 1.69 -}; - -float input2_data[ARRAY_SIZE] = -{ - 4.09, 3.02, 0.02, 8.91 -}; - -float verify_data[ARRAY_SIZE] = -{ - 1.65, 68.11, 20.84, 30.44 -}; -#endif -#if 0 -float input1_data[ARRAY_SIZE] = -{ - 1.0, 0.0, 0.0, 0.0 -}; - -float input2_data[ARRAY_SIZE] = -{ - 1.0, 0.0, 0.0, 1.0 -}; - -float verify_data[ARRAY_SIZE] = -{ - 1.0, 0.0, 0.0, 0.0 -}; -#endif - diff --git a/benchmarks/vec-matmul/matmul_gendata.pl b/benchmarks/vec-matmul/matmul_gendata.pl deleted file mode 100755 index c9d0ac7..0000000 --- a/benchmarks/vec-matmul/matmul_gendata.pl +++ /dev/null @@ -1,200 +0,0 @@ -#!/usr/bin/perl -w -#========================================================================== -# matmul_gendata.pl -# -# Author : Christopher Batten (cbatten@mit.edu) -# Date : April 29, 2005 -# -(our $usageMsg = <<'ENDMSG') =~ s/^\#//gm; -# -# Simple script which creates an input data set and the reference data -# for the matmul benchmark. -# -ENDMSG - -use strict "vars"; -use warnings; -no warnings("once"); -use Getopt::Long; - -#-------------------------------------------------------------------------- -# Command line processing -#-------------------------------------------------------------------------- - -our %opts; - -sub usage() -{ - - print "\n"; - print " Usage: matmul_gendata.pl [options] \n"; - print "\n"; - print " Options:\n"; - print " --help print this message\n"; - print " --size size of input data [1000]\n"; - print " --seed random seed [1]\n"; - print "$usageMsg"; - - exit(); -} - -sub processCommandLine() -{ - - $opts{"help"} = 0; - $opts{"size"} = 1000; - $opts{"seed"} = 1; - Getopt::Long::GetOptions( \%opts, 'help|?', 'size:i', 'seed:i' ) or usage(); - $opts{"help"} and usage(); - -} - -#-------------------------------------------------------------------------- -# Helper Functions -#-------------------------------------------------------------------------- - -sub printArray -{ - my $arrayName = $_[0]; - my $arrayRef = $_[1]; - - my $numCols = 20; - my $arrayLen = scalar(@{$arrayRef}); - - print "float ".$arrayName."[ARRAY_SIZE] = \n"; - print "{\n"; - - if ( $arrayLen <= $numCols ) { - print " "; - for ( my $i = 0; $i < $arrayLen; $i++ ) { - print sprintf("%3.2f",$arrayRef->[$i]); - if ( $i != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - else { - my $numRows = int($arrayLen/$numCols); - for ( my $j = 0; $j < $numRows; $j++ ) { - print " "; - for ( my $i = 0; $i < $numCols; $i++ ) { - my $index = $j*$numCols + $i; - print sprintf("%3.2f",$arrayRef->[$index]); - if ( $index != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - if ( $arrayLen > ($numRows*$numCols) ) { - print " "; - for ( my $i = 0; $i < ($arrayLen-($numRows*$numCols)); $i++ ) { - my $index = $numCols*$numRows + $i; - print sprintf("%3.2f",$arrayRef->[$index]); - if ( $index != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - } - - print "};\n\n"; -} - - - -#-------------------------------------------------------------------------- -# Matmul -#-------------------------------------------------------------------------- - -# http://answers.oreilly.com/topic/418-how-to-multiply-matrices-in-perl/ - -sub mmult { - my ($m1,$m2) = @_; - my ($m1rows,$m1cols) = matdim($m1); - my ($m2rows,$m2cols) = matdim($m2); - - my $result = [ ]; - my ($i, $j, $k); - - for $i (range($m1rows)) { - for $j (range($m2cols)) { - for $k (range($m1cols)) { - $result->[$i][$j] += $m1->[$i][$k] * $m2->[$k][$j]; - } - } - } - return $result; -} - -sub range { 0 .. ($_[0] - 1) } - - -sub veclen { - my $ary_ref = $_[0]; - my $type = ref $ary_ref; - if ($type ne "ARRAY") { die "$type is bad array ref for $ary_ref" } - return scalar(@$ary_ref); -} - -sub matdim { - my $matrix = $_[0]; - my $rows = veclen($matrix); - my $cols = veclen($matrix->[0]); - return ($rows, $cols); -} - -#-------------------------------------------------------------------------- -# Main -#-------------------------------------------------------------------------- - -sub main() -{ - - processCommandLine(); - srand($opts{"seed"}); - - # create random input arrays - my $mat_values1; - my $mat_values2; - for ( my $i = 0; $i < $opts{"size"}; $i++ ) { - for ( my $j = 0; $j < $opts{"size"}; $j++ ) { - $mat_values1->[$i][$j] = (rand(9)); - $mat_values2->[$i][$j] = (rand(9)); - } - } - - # perform matmul - my $mat_results = mmult( $mat_values1, $mat_values2 ); - - # translate 2d arrays to 1d-somethings (I don't know how to code in perl - Chris) - my @values1; - my @values2; - my @results; - for ( my $i = 0; $i < $opts{"size"}; $i++ ) { - for ( my $j = 0; $j < $opts{"size"}; $j++ ) { - my $value1 = $mat_values1->[$i][$j]; - my $value2 = $mat_values2->[$i][$j]; - my $result = $mat_results->[$i][$j]; - push( @values1, $value1 ); - push( @values2, $value2 ); - push( @results, $result ); - } - } - - print "\n\#define ARRAY_SIZE ".($opts{"size"}*$opts{"size"})." \n\n"; - print "\n\#define DIM_SIZE ".$opts{"size"}." \n\n"; - - printArray( "input1_data", \@values1 ); - printArray( "input2_data", \@values2 ); - printArray( "verify_data", \@results); - -} - -main(); - diff --git a/benchmarks/vec-matmul/vec_matmul_asm.S b/benchmarks/vec-matmul/vec_matmul_asm.S deleted file mode 100644 index a9cad53..0000000 --- a/benchmarks/vec-matmul/vec_matmul_asm.S +++ /dev/null @@ -1,345 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# matmul function (assembly version) -#----------------------------------------------------------------------------- - - -#-------------------------------------------------------------------------- -# Headers and Defines -#-------------------------------------------------------------------------- - -#include "pcr.h" - -# Here are some defines that make writing assembly code easier. - -# I'm using the knowledge that rLda will be placed in register a0, rA will be -# placed into register a1, etc., based on the calling convention for functions. - -#define rN a0 -#define rLda a0 -#define rA a1 -#define rB a2 -#define rC a3 -#define rATmp2 v0 -#define rBTmp2 s0 - - -# given vector-length -#define rVlen a7 - -# address of VT function -#define rVTAddr v1 -#define rTemp0 t0 - -# desired app vector length (number of elements to vectorize) -#define rNum t1 - -#define rATemp t2 -#define rBTemp t3 -#define rCTemp t4 -#define rI t5 -#define rJ s1 -#define rK s2 -#define rLda4 a4 -#define rK4 a5 -#define rI4 a6 - -# WARNING: do not write to the s0,...,s9 registers without first saving them to -# the stack! - -#-------------------------------------------------------------------------- -# void scalar_matmul_asm( int n, float a[], float b[], float c[] ) -#-------------------------------------------------------------------------- - - .text - .align 2 - .globl scalar_matmul_asm - .type scalar_matmul_asm,@function - -scalar_matmul_asm: - - # ***** Scalar Example ***** - - blez rLda, done # exit early if lda < 0 - - move rJ, zero -loopj: - move rI, zero -loopi: - move rK, zero -loopk: - mul rTemp0, rJ, rLda # calculate indices... I'm being SUPER naive here: - add rATemp, rK, rTemp0 # this could be a lot more clever! - slli rATemp, rATemp, 2 - add rATemp, rA, rATemp - - mul rTemp0, rK, rLda - add rBTemp, rI, rTemp0 - slli rBTemp, rBTemp, 2 - add rBTemp, rB, rBTemp - - mul rTemp0, rJ, rLda - add rCTemp, rI, rTemp0 - slli rCTemp, rCTemp, 2 - add rCTemp, rC, rCTemp - - flw f2, 0(rATemp) # again, I'm being very lazy... - # I can lift this out of the inner loop! - flw f3, 0(rBTemp) - flw f4, 0(rCTemp) - fmul.s f3, f2, f3 - fadd.s f4, f4, f3 - fsw f4, 0(rCTemp) -endk: - addi rK, rK, 1 - blt rK, rLda, loopk -endi: - addi rI, rI, 1 - blt rI, rLda, loopi -endj: - addi rJ, rJ, 1 - blt rJ, rLda, loopj -done: - ret - - -#-------------------------------------------------------------------------- -# void vt_matmul_asm( int n, float a[], float b[], float c[] ) -#-------------------------------------------------------------------------- - - - # ***** Vector-Thread Example ***** - - .globl vt_matmul_asm - .type vt_matmul_asm,@function - -vt_matmul_asm: - addi sp, sp, -24 - sd s0, 0(sp) - sd s1, 8(sp) - sd s2, 16(sp) - - - # turn on vector unit - setpcr status, SR_EV - - blez rLda, cpdone # exit early if lda < 0 - - - la rVTAddr, vtcode - slli rLda4, rLda, 2 - - #for starters ask for all the registers. We shouldn't need this many - #but we'll trim it when we have correctness in hand - vvcfgivl rVlen, rNum, 1, 5 - - - move rJ, zero -vec_loopj: - move rI, zero -vec_loopi: - slli rI4, rI, 2 - - sub rNum, rN, rI # book keeping - vsetvl rVlen, rNum # set the vector length - # rN is the desired (application) vector length - # rVlen is what vector length we were given - - ##################################### - # LOADS FOR C # - ##################################### - mul rTemp0, rJ, rLda4 - add rCTemp, rI4, rTemp0 - - add rCTemp, rC, rCTemp - vflw vf2, rCTemp - - add rCTemp, rCTemp, rLda4 - vflw vf4, rCTemp - - - ################################# - # address calculation lifts # - ################################# - mul rTemp0, rJ, rLda4 - add rATmp2, rA, rTemp0 - - add rBTmp2, rI4, rB - move rK, zero -vec_loopk: - slli rK4, rK, 2 - - ##################################### - # LOADS FOR A # - ##################################### - - add rATemp, rK4, rATmp2 - vflstw vf0, rATemp, zero - - add rATemp, rATemp, rLda4 - vflstw vf3, rATemp, zero - - - ##################################### - # LOADS FOR B # - ##################################### - mul rTemp0, rK, rLda4 - add rBTemp, rBTmp2, rTemp0 - vflw vf1, rBTemp - vf 0(rVTAddr) - - ##################################### - # LOADS FOR A # - ##################################### - add rATemp, rK4, rATmp2 - addi rATemp, rATemp, 4 - vflstw vf0, rATemp, zero - - add rATemp, rATemp, rLda4 - vflstw vf3, rATemp, zero - - - ##################################### - # LOADS FOR B # - ##################################### - add rBTemp, rBTemp, rLda4 - vflw vf1, rBTemp - vf 0(rVTAddr) - - ##################################### - # LOADS FOR A # - ##################################### - add rATemp, rK4, rATmp2 - addi rATemp, rATemp, 8 - vflstw vf0, rATemp, zero - - add rATemp, rATemp, rLda4 - vflstw vf3, rATemp, zero - - - ##################################### - # LOADS FOR B # - ##################################### - add rBTemp, rBTemp, rLda4 - vflw vf1, rBTemp - vf 0(rVTAddr) - - - ##################################### - # LOADS FOR A # - ##################################### - add rATemp, rK4, rATmp2 - addi rATemp, rATemp, 12 - vflstw vf0, rATemp, zero - - add rATemp, rATemp, rLda4 - vflstw vf3, rATemp, zero - - - ##################################### - # LOADS FOR B # - ##################################### - add rBTemp, rBTemp, rLda4 - vflw vf1, rBTemp - vf 0(rVTAddr) - -vec_endk: - addi rK, rK, 4 - blt rK, rLda, vec_loopk - -vec_endi: - ##################################### - # STORES FOR C # - ##################################### - vfsw vf4, rCTemp - sub rCTemp, rCTemp, rLda4 - vfsw vf2, rCTemp - - add rI, rI, rVlen - blt rI, rLda, vec_loopi -vec_endj: - addi rJ, rJ, 2 -# fence.v.l - blt rJ, rLda, vec_loopj - - -cpdone: - fence.v.l - ld s0, 0(sp) - ld s1, 8(sp) - ld s2, 16(sp) - addi sp, sp, 24 - - - ret - -vtcode: - # ADD YOUR VECTOR-ELEMENT CODE HERE ... - - #TODO: hit this with a fused multiply add. - - fmadd.s f2, f0, f1, f2 - fmadd.s f4, f3, f1, f4 - #fmadd.s f6, f5, f1, f6 - #fmadd.s f8, f7, f1, f8 - - - #fmul.s f1, f0, f1 - #fadd.s f2, f2, f1 - stop - -transpose: - # turn on vector unit - setpcr status, SR_EV - - - blez rLda, cpdone # exit early if lda < 0 - vvcfgivl rVlen, rNum, 1, 1 - - move rI, zero -tloopi: - sub rNum, rLda, rI - vsetvl rVlen, rNum - - move rJ, zero -tloopj: - - mul rTemp0, rJ, rLda - add rATemp, rI, rTemp0 - slli rATemp, rATemp, 2 - add rATemp, rA, rATemp - - mul rTemp0, rI, rLda - add rBTemp, rJ, rTemp0 - slli rBTemp, rBTemp, 2 - add rBTemp, rB, rBTemp - - #flw f0, 0(rBTemp) - #fsw f0, 0(rATemp) - vflstw vf0, rBTemp, rLda4 - vfsw vf0, rATemp - -tendj: - addi rJ, rJ, 1 - blt rJ, rLda, tloopj -tendi: - #addi rI, rI, 1 - add rI, rI, rVlen - blt rI, rLda, tloopi - - ret - # The C code uses a jalr instruction to call this function - # so we can use a jr to return back to where the function - # was called. Also known as "ret", for "return". - - ret - - - -##################################### -# NOPS TO AVOID OVERPREFETCH # -##################################### -# srli rTemp0, rLda, 4 -#nop_lp: addi rTemp0, rTemp0, -1 -# bgez rTemp0, nop_lp diff --git a/benchmarks/vec-matmul/vec_matmul_main.c b/benchmarks/vec-matmul/vec_matmul_main.c deleted file mode 100644 index 9554da8..0000000 --- a/benchmarks/vec-matmul/vec_matmul_main.c +++ /dev/null @@ -1,207 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// Vector-Thread Vector Matrix Multiply benchmark -//-------------------------------------------------------------------------- -// -// This benchmark multiplies two 2-D arrays together and writes the results to -// a third vector. The input data (and reference data) should be generated -// using the matmul_gendata.pl perl script and dumped to a file named -// dataset.h. - -#include "util.h" - -// Choose which implementation you wish to test... but leave only one on! -// (only the first one will be executed). -//#define SCALAR_C -//#define SCALAR_ASM -#define VT_ASM - -//-------------------------------------------------------------------------- -// Input/Reference Data - -//#include "dataset_test.h" -#include "dataset.h" - -//-------------------------------------------------------------------------- -// Helper functions - -int verify( int n, float test[], float correct[] ) -{ - int i; - for ( i = 0; i < n; i++ ) { - if ( test[i] > 1.02*correct[i] - || test[i] < 0.98*correct[i]) { -#if HOST_DEBUG - printf(" test[%d] : %3.2f\n", i, test[i]); - printf(" corr[%d] : %3.2f\n", i, correct[i]); -#endif - // tell us which index fails + 2 - // (so that if i==0,i==1 fails, we don't - // think it was a 'not-finished yet' or pass) - return i+10; - } - } - return 1; -} - -void finishTest( int correct, long long num_cycles, long long num_retired ) -{ - int toHostValue = correct; -#if HOST_DEBUG - if ( toHostValue == 1 ) - printf( "*** PASSED ***\n" ); - else - printf( "*** FAILED *** (tohost = %d)\n", toHostValue ); - exit(0); -#else - // we no longer run in -testrun mode, which means we can't use - // the tohost register to communicate "test is done" and "test results" - // so instead we will communicate through print* functions! - if ( correct == 1 ) - { - printstr( "*** PASSED *** (num_cycles = 0x" ); - printhex(num_cycles); - printstr( ", num_inst_retired = 0x"); - printhex(num_retired); - printstr( ")\n" ); - } - else - { - printstr( "*** FAILED *** (num_cycles = 0x"); - printhex(num_cycles); - printstr( ", num_inst_retired = 0x"); - printhex(num_retired); - printstr( ")\n" ); - } - exit(); -#endif -} - - -// deprecated - cr10/stats-enable register no longer exists -void setStats( int enable ) -{ -#if ( !HOST_DEBUG && SET_STATS ) - asm( "mtpcr %0, cr10" : : "r" (enable) ); -#endif -} - -long long getCycles() -{ - long long cycles = 1337; -#if ( !HOST_DEBUG && SET_STATS ) - __asm__ __volatile__( "rdcycle %0" : "=r" (cycles) ); -#endif - return cycles; -} - -long long getInstRetired() -{ - long long inst_retired = 1338; -#if ( !HOST_DEBUG && SET_STATS ) - __asm__ __volatile__( "rdinstret %0" : "=r" (inst_retired) ); -#endif - return inst_retired; -} - -//-------------------------------------------------------------------------- -// matmul function - -// scalar C implementation -void matmul(const int lda, const float A[], const float B[], float C[] ) -{ - int i, j, k; - - for ( j = 0; j < lda; j++ ) - for ( i = 0; i < lda; i++ ) - { - float cij = C[i + j*lda]; - for ( k = 0; k < lda; k++ ) - { - cij += A[j*lda + k] * B[k*lda + i]; - } - C[i + j*lda] = cij; - } -} - - -// assembly implementations can be found in *_asm.S - -//-------------------------------------------------------------------------- -// Main - -int main( int argc, char* argv[] ) -{ - int i,j; - long long start_cycles = 0; - long long stop_cycles = 0; - long long num_cycles; - long long start_retired = 0; - long long stop_retired = 0; - long long num_retired; - - float results_data[ARRAY_SIZE]; - for ( i = 0; i < DIM_SIZE; i++ ) - for ( j = 0; j < DIM_SIZE; j++ ) - results_data[i + j*DIM_SIZE] = 0.0f; - - // Output the input array - -#if HOST_DEBUG - printArray( "input1", ARRAY_SIZE, input1_data ); - printArray( "input2", ARRAY_SIZE, input2_data ); - printArray( "verify", ARRAY_SIZE, verify_data ); - printArray( "results", ARRAY_SIZE, results_data ); -#endif - - // -------------------------------------------------- - // If needed we preallocate everything in the caches - -#if PREALLOCATE - - - -#endif - - // -------------------------------------------------- - // Do the matmul - start_cycles = getCycles(); - start_retired = getInstRetired(); - -#ifdef SCALAR_C - matmul( DIM_SIZE, input1_data, input2_data, results_data ); -#else -#ifdef SCALAR_ASM - #if HOST_DEBUG==0 - scalar_matmul_asm( DIM_SIZE, input1_data, input2_data, results_data ); - #endif -#else -#ifdef VT_ASM - #if HOST_DEBUG==0 - vt_matmul_asm( DIM_SIZE, input1_data, input2_data, results_data ); - #endif -#endif -#endif -#endif - - - stop_cycles = getCycles(); - stop_retired = getInstRetired(); - num_cycles = stop_cycles - start_cycles; - num_retired = stop_retired - start_retired; - - - // -------------------------------------------------- - // Print out the results - -#if HOST_DEBUG - printArray( "results", ARRAY_SIZE, results_data ); -#endif - - - // -------------------------------------------------- - // Check the results - int correct = verify( ARRAY_SIZE, results_data, verify_data ); - finishTest(correct, num_cycles, num_retired); -} diff --git a/benchmarks/vec-vvadd/bmark.mk b/benchmarks/vec-vvadd/bmark.mk deleted file mode 100644 index 78ebff2..0000000 --- a/benchmarks/vec-vvadd/bmark.mk +++ /dev/null @@ -1,30 +0,0 @@ -#======================================================================= -# UCB CS250 Makefile fragment for benchmarks -#----------------------------------------------------------------------- -# -# Each benchmark directory should have its own fragment which -# essentially lists what the source files are and how to link them -# into an riscv and/or host executable. All variables should include -# the benchmark name as a prefix so that they are unique. -# - -vec_vvadd_c_src = \ - vec_vvadd_main.c \ - -vec_vvadd_riscv_src = \ - crt.S \ - vec_vvadd_asm.S - -vec_vvadd_c_objs = $(patsubst %.c, %.o, $(vec_vvadd_c_src)) -vec_vvadd_riscv_objs = $(patsubst %.S, %.o, $(vec_vvadd_riscv_src)) - -vec_vvadd_host_bin = vec-vvadd.host -$(vec_vvadd_host_bin) : $(vec_vvadd_c_src) - $(HOST_COMP) $^ -o $(vec_vvadd_host_bin) - -vec_vvadd_riscv_bin = vec-vvadd.riscv -$(vec_vvadd_riscv_bin) : $(vec_vvadd_c_objs) $(vec_vvadd_riscv_objs) - $(RISCV_LINK) $(RISCV_LINK_SYSCALL) $(vec_vvadd_c_objs) $(vec_vvadd_riscv_objs) -o $(vec_vvadd_riscv_bin) - -junk += $(vec_vvadd_c_objs) $(vec_vvadd_riscv_objs) \ - $(vec_vvadd_host_bin) $(vec_vvadd_riscv_bin) diff --git a/benchmarks/vec-vvadd/dataset.h b/benchmarks/vec-vvadd/dataset.h deleted file mode 100644 index 976896f..0000000 --- a/benchmarks/vec-vvadd/dataset.h +++ /dev/null @@ -1,173 +0,0 @@ -// See LICENSE for license details. - - -#define DATA_SIZE 1024 - -float input1_data[DATA_SIZE] = -{ - 41.59, 833.98, 564.92, 187.40, 749.75, 350.86, 132.42, 949.90, 584.06, 805.70, 621.44, 6.57, 931.73, 890.19, 392.50, 694.30, 961.50, 110.85, 116.64, 296.64, - 426.15, 314.26, 659.38, 774.03, 319.50, 678.95, 875.15, 376.99, 474.52, 938.39, 539.64, 569.21, 203.10, 280.59, 759.17, 606.49, 511.73, 657.85, 195.14, 81.76, - 267.13, 229.11, 337.80, 944.31, 902.33, 241.76, 913.03, 826.41, 933.10, 985.95, 195.94, 960.23, 566.85, 350.87, 649.08, 657.11, 181.07, 111.93, 859.03, 65.38, - 288.41, 349.32, 141.62, 905.27, 886.09, 264.13, 576.69, 979.62, 761.15, 241.01, 478.77, 499.56, 403.08, 222.09, 444.00, 721.13, 676.11, 317.98, 224.02, 937.91, - 288.16, 119.49, 615.12, 606.02, 389.63, 351.17, 455.08, 278.19, 367.94, 358.65, 584.29, 62.81, 985.38, 403.31, 346.66, 517.64, 559.24, 908.23, 775.53, 255.22, - 778.76, 598.70, 143.67, 33.87, 125.22, 941.32, 933.58, 799.68, 553.00, 431.48, 648.92, 952.26, 287.81, 19.55, 49.85, 86.34, 95.37, 441.32, 587.26, 614.94, - 382.15, 280.93, 808.48, 971.60, 819.34, 344.75, 450.92, 512.61, 965.23, 347.78, 808.67, 882.45, 537.55, 946.57, 701.25, 356.05, 567.96, 891.59, 22.08, 568.05, - 665.92, 423.06, 434.34, 158.95, 2.47, 84.01, 247.70, 49.41, 435.28, 792.95, 869.12, 486.44, 414.24, 369.14, 548.71, 518.09, 888.38, 682.27, 284.83, 264.53, - 499.48, 290.72, 897.15, 215.27, 731.10, 688.62, 251.21, 786.26, 555.77, 302.26, 528.37, 544.63, 322.31, 947.49, 287.49, 824.15, 304.91, 788.79, 733.63, 959.89, - 366.53, 722.70, 294.29, 975.54, 653.47, 748.94, 91.37, 378.81, 105.56, 102.96, 381.89, 651.77, 825.56, 840.65, 356.91, 148.28, 54.55, 140.19, 955.46, 343.09, - 533.74, 757.52, 521.69, 837.60, 592.30, 13.14, 173.27, 63.12, 121.08, 133.74, 758.23, 372.02, 951.71, 39.51, 129.91, 110.98, 847.87, 437.05, 255.51, 269.43, - 409.58, 628.32, 399.16, 549.49, 753.43, 564.11, 171.44, 19.41, 727.43, 501.57, 777.90, 43.09, 753.99, 81.39, 202.47, 853.24, 153.74, 760.34, 357.21, 943.33, - 922.66, 328.36, 496.72, 442.71, 516.93, 641.63, 276.71, 786.16, 113.96, 842.51, 907.08, 275.40, 237.13, 32.98, 784.54, 565.19, 357.36, 803.66, 819.14, 751.19, - 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340.41, 910.73, 206.71, 572.95, 505.78, 973.87, 961.61, 354.74, 627.25, 849.72, 971.69, 910.80, 410.29, 770.61, 63.75, 874.84, 396.21, 482.65, 619.93, 646.52, - 557.70, 328.81, 67.74, 884.16, 512.52, 972.25, 6.13, 513.12, 882.90, 562.88, 764.78, 366.50, 506.01, 786.96, 831.46, 382.69, 638.33, 452.86, 72.80, 83.99, - 59.48, 932.56, 929.17, 924.31, 961.79, 69.09, 797.94, 985.49, 854.03, 885.08, 600.77, 389.36, 232.77, 793.58, 179.91, 773.67, 689.88, 775.80, 494.89, 139.65, - 234.41, 431.79, 780.34, 371.94, 22.47, 653.95, 741.81, 815.30, 429.00, 139.33, 603.92, 315.04, 344.80, 889.48, 317.27, 260.28, 861.63, 377.78, 511.76, 304.06, - 70.19, 35.87, 854.09, 576.98, 490.35, 326.55, 303.50, 431.21, 813.10, 708.96, 388.67, 962.18, 967.95, 442.52, 49.02, 831.49, 251.65, 321.36, 741.45, 179.51, - 176.27, 117.00, 523.73, 764.26, 952.82, 704.67, 531.80, 804.94, 23.61, 611.10, 846.79, 375.26, 854.69, 971.77, 24.05, 639.17, 318.66, 723.53, 662.84, 647.47, - 281.11, 158.85, 294.58, 885.85, 734.06, 866.60, 471.06, 296.09, 673.55, 472.93, 439.09, 5.93, 155.39, 506.79, 948.50, 600.40, 445.21, 222.05, 784.59, 349.77, - 943.37, 150.14, 366.16, 444.22, 604.60, 720.40, 340.70, 972.58, 911.45, 321.49, 435.22, 50.43, 78.96, 761.04, 950.33, 238.41, 27.06, 226.17, 201.43, 176.53, - 877.51, 450.94, 879.63, 99.89, 143.28, 31.66, 812.36, 771.31, 527.29, 488.63, 797.10, 194.25, 293.72, 966.52, 276.35, 345.26, 413.02, 197.52, 386.04, 116.36, - 322.72, 680.35, 538.15, 554.00, 960.31, 874.79, 48.72, 506.93, 898.24, 539.71, 495.50, 764.01, 805.12, 286.44, 432.09, 836.98, 192.15, 825.36, 778.42, 586.55, - 359.37, 352.70, 746.78, 11.34, 749.69, 5.98, 408.76, 643.32, 441.94, 368.15, 97.74, 169.62, 359.25, 527.49, 672.31, 69.39, 880.66, 298.11, 300.84, 327.09, - 923.83, 829.55, 816.51, 497.50, 243.91, 981.12, 917.21, 713.38, 653.91, 503.75, 406.65, 543.57, 108.87, 304.66, 464.10, 954.74, 86.37, 802.71, 446.02, 28.16, - 539.76, 655.37, 28.71, 470.59, 735.85, 941.08, 610.37, 451.33, 672.34, 237.47, 766.04, 713.35, 409.69, 869.06, 186.75, 475.83, 568.73, 44.08, 997.88, 139.85, - 456.29, 470.05, 566.52, 408.79 -}; - -float verify_data[DATA_SIZE] = -{ - 495.63, 1169.63, 566.69, 1176.85, 1115.65, 923.63, 196.52, 1103.31, 800.44, 946.03, 832.12, 579.30, 1271.72, 1483.47, 1290.93, 922.67, 973.54, 994.06, 866.81, 942.68, - 926.59, 750.61, 1361.22, 1586.49, 1300.84, 829.78, 1571.21, 941.26, 746.74, 1197.19, 1186.78, 1078.26, 291.58, 984.55, 1429.12, 981.74, 1063.38, 1594.80, 787.78, 650.92, - 1219.28, 1030.07, 922.15, 1587.41, 1270.39, 730.77, 1241.89, 1139.44, 1525.85, 1374.42, 739.91, 1609.95, 1546.39, 1348.24, 1463.38, 736.32, 389.61, 1110.21, 1488.91, 912.76, - 992.84, 1346.40, 395.18, 1620.78, 1316.18, 679.69, 1115.23, 1679.96, 765.68, 735.85, 578.79, 1364.33, 1096.91, 638.70, 740.87, 1007.04, 1297.08, 396.49, 575.61, 1478.78, - 934.92, 289.41, 1142.74, 895.34, 1185.93, 1152.77, 1175.57, 1037.12, 1113.42, 450.84, 1573.31, 334.07, 1838.73, 1191.90, 878.61, 740.34, 1020.32, 1149.83, 1133.92, 587.39, - 1463.34, 1338.72, 589.95, 345.84, 868.80, 1498.73, 1412.65, 1357.10, 1478.39, 1227.79, 1006.65, 1843.31, 953.88, 534.37, 607.77, 956.35, 948.69, 881.54, 648.39, 1293.73, - 778.68, 290.54, 825.76, 1142.18, 1110.55, 725.01, 987.02, 698.44, 1882.36, 887.56, 1791.84, 1770.09, 592.34, 1558.82, 1652.77, 835.96, 719.46, 899.23, 664.05, 903.48, - 1396.04, 518.20, 1162.70, 439.42, 397.65, 772.71, 1158.74, 526.29, 1250.34, 1522.57, 1134.26, 614.25, 650.49, 583.54, 729.60, 524.55, 1391.95, 1278.39, 458.49, 908.20, - 846.41, 890.50, 966.06, 1065.12, 1389.53, 1308.07, 372.88, 918.11, 1384.40, 969.38, 962.13, 1032.60, 1076.19, 1073.28, 914.24, 838.56, 315.50, 1192.41, 839.63, 1663.34, - 1184.70, 1686.79, 700.69, 1849.94, 1509.85, 835.52, 151.84, 1039.76, 773.51, 256.03, 503.21, 749.88, 1238.18, 1076.99, 369.33, 571.92, 1019.76, 356.41, 1576.64, 704.75, - 1455.51, 1472.74, 1169.31, 1137.32, 1479.12, 695.76, 209.72, 557.09, 672.13, 670.97, 1728.14, 1015.15, 1386.02, 454.90, 433.10, 549.65, 1708.33, 640.17, 734.17, 1257.85, - 1084.79, 1347.56, 1389.80, 887.96, 1204.24, 1197.28, 326.78, 666.15, 1180.43, 928.80, 1287.07, 1032.07, 1180.09, 94.13, 685.73, 995.48, 493.52, 1151.15, 408.17, 1114.49, - 1524.20, 433.83, 1465.62, 563.97, 1396.91, 723.51, 1147.02, 1386.71, 717.25, 1714.24, 1794.58, 885.95, 641.78, 267.14, 1530.24, 1091.63, 632.86, 1245.24, 1046.10, 1504.05, - 1223.69, 811.73, 1168.43, 656.17, 765.15, 1217.91, 95.02, 650.84, 419.21, 649.88, 1116.37, 1608.19, 700.41, 1219.33, 1270.55, 889.25, 532.70, 1062.99, 1598.94, 1119.37, - 1178.37, 1441.16, 723.46, 1398.57, 480.94, 961.90, 1060.27, 552.90, 582.30, 371.55, 391.32, 1030.28, 769.01, 945.25, 1492.23, 941.67, 1179.47, 1229.81, 311.71, 793.56, - 964.38, 814.96, 522.52, 779.87, 972.03, 943.17, 465.51, 923.71, 1243.30, 1061.68, 193.53, 22.70, 1464.04, 900.06, 872.18, 1173.28, 1102.63, 1350.75, 924.32, 702.08, - 1210.63, 1291.41, 1146.94, 478.30, 817.32, 1526.45, 1595.77, 1059.94, 459.94, 1291.29, 230.02, 643.22, 734.35, 163.08, 1224.35, 1579.24, 739.99, 1853.34, 1493.65, 1205.98, - 986.54, 176.68, 1186.45, 833.02, 724.94, 1406.38, 960.15, 1115.99, 713.18, 541.81, 1460.84, 1529.83, 1204.00, 1205.70, 799.72, 380.19, 1368.62, 1609.47, 840.13, 679.74, - 1506.54, 633.28, 866.21, 327.23, 218.80, 1072.27, 572.78, 243.33, 1205.41, 202.56, 1448.61, 1638.72, 1584.11, 1080.07, 407.61, 199.82, 441.20, 1551.94, 965.44, 795.64, - 959.34, 555.31, 488.27, 406.73, 701.51, 1203.74, 1799.83, 1072.04, 538.08, 1203.05, 1066.74, 1159.37, 1395.75, 1338.61, 1009.44, 761.86, 1282.53, 1265.02, 496.10, 850.27, - 1052.65, 396.25, 1087.04, 1744.14, 1094.86, 1516.72, 1453.94, 1616.13, 1478.13, 1737.48, 522.87, 1072.44, 1174.25, 1552.93, 881.42, 1392.32, 723.46, 1180.41, 1342.61, 701.77, - 1164.72, 870.50, 562.36, 1244.36, 1173.48, 636.73, 1364.08, 1035.71, 1161.69, 775.92, 840.61, 1401.61, 1621.91, 668.97, 354.52, 1419.21, 1172.70, 647.51, 413.69, 876.51, - 642.38, 1212.78, 818.58, 1231.63, 1115.00, 1562.69, 1664.33, 1067.59, 102.18, 1246.92, 1629.75, 1728.50, 936.44, 830.21, 511.66, 1256.62, 1162.52, 1680.10, 200.55, 1287.67, - 945.54, 427.81, 1202.72, 384.08, 1592.24, 239.35, 405.04, 1191.17, 937.99, 897.12, 1060.18, 1005.41, 1723.60, 611.18, 990.11, 612.63, 1202.58, 699.39, 1590.74, 841.09, - 1903.33, 643.97, 650.04, 938.41, 996.74, 1554.70, 960.19, 1789.12, 1764.47, 843.99, 1493.67, 1089.42, 1570.66, 807.37, 1262.68, 833.91, 1155.12, 970.59, 1124.96, 974.72, - 1338.35, 311.26, 1574.08, 712.10, 1061.67, 987.70, 1020.03, 737.85, 264.38, 889.41, 1225.92, 773.42, 1365.73, 1150.43, 442.54, 939.08, 1064.75, 873.07, 273.93, 902.05, - 1764.15, 1499.80, 583.52, 1324.39, 1313.75, 741.33, 618.68, 914.59, 693.50, 1538.31, 1154.48, 327.54, 1018.09, 1397.45, 746.21, 328.09, 586.35, 1358.57, 1132.98, 947.89, - 769.17, 1100.19, 533.13, 894.29, 1313.62, 1001.59, 874.31, 1174.35, 1048.89, 564.06, 93.33, 809.48, 1129.55, 1314.88, 1304.70, 572.27, 1775.82, 1267.01, 1118.51, 978.19, - 959.40, 1089.10, 1405.59, 1203.46, 679.05, 1484.27, 1682.75, 1251.06, 377.47, 1735.35, 693.27, 530.23, 575.65, 1061.01, 955.49, 1021.06, 1095.51, 1294.81, 910.64, 427.66, - 1162.01, 1460.55, 796.81, 1079.52, 315.24, 1030.87, 648.27, 983.92, 1378.95, 112.53, 699.70, 1136.13, 753.89, 1400.42, 1087.55, 216.02, 947.95, 1562.12, 1025.12, 893.25, - 715.59, 664.46, 599.00, 1347.54, 165.38, 1487.48, 1004.37, 1076.79, 1007.48, 906.74, 1383.74, 823.94, 537.97, 1051.54, 1459.79, 1325.02, 1064.35, 754.49, 896.01, 669.95, - 1350.57, 662.43, 716.21, 1327.48, 1100.74, 549.02, 1224.82, 382.59, 743.32, 638.50, 647.15, 1116.38, 636.23, 1258.26, 181.62, 975.32, 1384.29, 809.34, 1338.34, 908.77, - 222.96, 901.00, 1267.96, 1341.91, 1342.76, 1573.69, 1312.25, 397.71, 716.94, 743.90, 1275.29, 1573.61, 1218.13, 1442.78, 777.53, 1886.74, 928.38, 1064.95, 682.57, 1389.99, - 137.80, 1581.75, 870.93, 183.08, 979.51, 1741.65, 1598.00, 325.19, 1688.71, 1388.89, 1350.48, 1605.55, 1216.06, 1443.41, 448.51, 816.99, 398.15, 620.33, 1695.69, 77.84, - 1003.98, 696.49, 1102.40, 860.31, 797.44, 1090.82, 1080.36, 1614.18, 1243.54, 602.96, 683.61, 1348.56, 723.06, 1480.29, 176.04, 192.82, 1945.34, 484.10, 736.05, 778.60, - 878.83, 1253.86, 1250.40, 1319.50, 698.36, 1214.66, 991.67, 1443.62, 1284.79, 1230.94, 1526.71, 1271.40, 1356.76, 1534.22, 428.41, 788.58, 1681.33, 827.11, 1243.77, 1340.54, - 813.27, 1095.47, 833.86, 1043.78, 480.13, 1482.43, 1402.35, 1031.26, 1148.11, 1531.28, 597.82, 821.05, 1338.69, 1314.80, 649.53, 1578.87, 1035.26, 1318.49, 922.49, 1788.10, - 970.84, 502.20, 253.02, 706.77, 707.80, 695.45, 1184.45, 1098.58, 1235.92, 434.17, 642.81, 998.40, 1337.46, 1422.00, 1641.30, 695.39, 1137.30, 1151.58, 1469.27, 813.26, - 1161.87, 1655.05, 207.04, 1167.83, 783.70, 1093.98, 1642.08, 1112.26, 1182.71, 1697.44, 1489.02, 1289.98, 916.05, 1675.47, 309.95, 1117.86, 790.35, 913.24, 834.63, 891.03, - 1082.40, 728.59, 240.69, 1188.95, 1132.99, 1567.14, 541.47, 1211.96, 1042.48, 1313.06, 1574.58, 821.21, 582.01, 880.12, 999.23, 399.25, 1491.61, 947.72, 397.45, 162.75, - 111.60, 1045.00, 940.01, 1266.90, 1692.45, 749.80, 1085.51, 1946.78, 946.25, 1511.17, 1513.31, 1005.75, 1093.23, 1537.69, 924.45, 1252.27, 1305.19, 1283.97, 1409.40, 950.03, - 523.06, 1406.31, 909.64, 953.01, 571.43, 1522.05, 1723.30, 1085.33, 1052.03, 792.36, 1230.06, 1305.36, 731.50, 1213.35, 790.13, 424.94, 1101.40, 567.48, 1376.87, 536.06, - 426.39, 188.71, 1679.97, 905.57, 880.88, 1174.62, 342.05, 834.11, 1429.95, 1255.03, 595.08, 964.68, 1751.30, 1332.67, 864.20, 1663.44, 917.26, 731.89, 835.65, 426.11, - 598.39, 328.55, 1198.86, 774.17, 1327.00, 1131.50, 596.69, 858.45, 782.24, 1422.98, 1347.43, 813.23, 1190.64, 1299.97, 261.53, 1054.87, 787.13, 1408.05, 1228.08, 953.22, - 730.28, 756.75, 431.44, 1768.64, 1117.16, 1804.65, 739.66, 411.11, 1581.98, 523.18, 1391.70, 372.29, 552.46, 764.22, 1180.11, 1267.78, 480.53, 1213.03, 1227.84, 563.46, - 1332.42, 163.53, 987.30, 497.06, 1217.30, 1655.09, 1294.21, 1801.51, 1373.76, 943.23, 1247.88, 573.11, 751.33, 818.42, 1263.77, 590.93, 82.72, 1198.69, 954.88, 592.85, - 1757.16, 1315.57, 1452.03, 263.52, 864.34, 43.90, 1455.87, 1278.42, 1495.61, 1270.29, 1637.27, 436.48, 924.10, 1777.09, 1071.38, 781.19, 1298.99, 797.01, 1082.87, 760.34, - 415.80, 1390.71, 1323.19, 666.33, 1541.97, 887.62, 971.73, 1122.91, 1551.00, 899.40, 757.40, 997.65, 1414.61, 972.90, 971.97, 955.10, 752.96, 1564.64, 798.87, 904.46, - 1335.73, 926.08, 1133.48, 783.88, 1413.28, 510.87, 620.83, 1532.29, 1349.13, 788.82, 834.80, 686.17, 384.31, 747.41, 1470.31, 786.32, 1332.86, 990.15, 984.81, 786.91, - 1739.38, 1153.33, 1429.27, 745.05, 360.07, 1333.72, 1198.64, 1452.21, 944.04, 1413.41, 1051.90, 1169.43, 1041.60, 524.85, 1149.41, 1327.75, 962.41, 1449.32, 858.12, 983.77, - 1203.83, 1505.59, 812.11, 863.24, 1443.57, 1363.27, 1133.76, 1133.62, 709.97, 393.53, 809.24, 1481.34, 534.41, 1418.23, 1001.29, 727.08, 783.39, 256.43, 1570.59, 1038.65, - 1412.63, 1078.93, 1217.72, 843.61 -}; - diff --git a/benchmarks/vec-vvadd/dataset_test.h b/benchmarks/vec-vvadd/dataset_test.h deleted file mode 100644 index 8b7ec21..0000000 --- a/benchmarks/vec-vvadd/dataset_test.h +++ /dev/null @@ -1,20 +0,0 @@ -// See LICENSE for license details. - - -#define DATA_SIZE 4 - -float input1_data[DATA_SIZE] = -{ - 41.59, 833.98, 564.92, 187.40 -}; - -float input2_data[DATA_SIZE] = -{ - 454.04, 335.65, 1.77, 989.44 -}; - -float verify_data[DATA_SIZE] = -{ - 495.63, 1169.63, 566.69, 1176.85 -}; - diff --git a/benchmarks/vec-vvadd/vec_vvadd_asm.S b/benchmarks/vec-vvadd/vec_vvadd_asm.S deleted file mode 100644 index c4d0534..0000000 --- a/benchmarks/vec-vvadd/vec_vvadd_asm.S +++ /dev/null @@ -1,110 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# vvadd function (assembly version) -#----------------------------------------------------------------------------- - - -#-------------------------------------------------------------------------- -# Headers and Defines -#-------------------------------------------------------------------------- - -# Here are some defines that make writing assembly code easier. - -# I'm using the knowledge that rN will be placed in register a0, rA will be -# placed into register a1, etc., based on the calling convention for functions. - -#define rN a0 -#define rA a1 -#define rB a2 -#define rC a3 - -#define rVLen a4 - -# WARNING: do not write to the s0,...,s9 registers without first saving them to -# the stack. - -#-------------------------------------------------------------------------- -# void scalar_vvadd_asm( int n, float a[], float b[], float c[] ) -#-------------------------------------------------------------------------- - - .text - .align 2 - .globl scalar_vvadd_asm - .type scalar_vvadd_asm,@function - -scalar_vvadd_asm: - - # ***** Scalar Example ***** - - beq rN, zero, done # exit early if n == 0 - -loop: - flw f2, 0(rA) - flw f3, 0(rB) - fadd.s f2, f2, f3 - fsw f2, 0(rC) - addi rN, rN, -1 - addi rA, rA, 4 - addi rB, rB, 4 - addi rC, rC, 4 - bne rN, zero, loop -done: - ret - - -#-------------------------------------------------------------------------- -# void vt_vvadd_asm( int n, float a[], float b[], float c[] ) -#-------------------------------------------------------------------------- - - - # ***** Vector-Thread Example ***** - - .globl vt_vvadd_asm - .type vt_vvadd_asm,@function - -vt_vvadd_asm: - - beq rN, zero, cpdone - la a5, vtcode - - # First, configure the vector unit. - # rd (given vlen), desired vlen, num of x-regs, num of f-regs - # For vvadd, we do not need to use any x-registers, and only two - # floating point registers. By using fewer registers, hwacha can give us a longer vector length! - # But make sure to use registers starting from x0, f0! - # WARNING: there is a BUG if you tell it you want 0 registers of any type! - # So here I'm asking for 1 x-register, even though I don't use any of them. - vvcfgivl rVLen, rN, 1, 2 - - -stripmineloop: - vsetvl rVLen, rN # set the vector length - # rN is the desired (application) vector length - # rVLen is what vector length we were given - - vflw vf0, rA # vector loads - vflw vf1, rB - vf 0(a5) # jump to vector-fetch code - vfsw vf0, rC # vector store - - sub rN, rN, rVLen # book keeping - slli a6, rVLen, 2 # turn num_elements into num_bytes - add rA, rA, a6 - add rB, rB, a6 - add rC, rC, a6 - bne rN, zero, stripmineloop - -cpdone: - fence.v.l # make stores visible to the control processor - ret - -vtcode: - fadd.s f0, f0, f1 - stop - - # The C code uses a jalr instruction to call this function - # so we can use a jr to return back to where the function - # was called. Also known as "ret", for "return". - - ret diff --git a/benchmarks/vec-vvadd/vec_vvadd_main.c b/benchmarks/vec-vvadd/vec_vvadd_main.c deleted file mode 100644 index 6b53871..0000000 --- a/benchmarks/vec-vvadd/vec_vvadd_main.c +++ /dev/null @@ -1,200 +0,0 @@ -// See LICENSE for license details. - -//************************************************************************** -// Vector-Thread Vector-vector add benchmark -//-------------------------------------------------------------------------- -// -// This benchmark uses adds to vectors and writes the results to a third -// vector. The input data (and reference data) should be generated using the -// vvadd_gendata.pl perl script and dumped to a file named dataset.h. - -// Choose which implementation you wish to test... but leave only one on! -// (only the first one will be executed). -//#define SCALAR_C -//#define SCALAR_ASM -#define VT_ASM - -//-------------------------------------------------------------------------- -// Input/Reference Data - -//#include "dataset_test.h" -#include "dataset.h" - -//-------------------------------------------------------------------------- -// Helper functions - -int verify( int n, float test[], float correct[] ) -{ - int i; - for ( i = 0; i < n; i++ ) { -// if ( test[i] != correct[i] ) { - if ( test[i] > 1.02*correct[i] - || test[i] < 0.98*correct[i]) { -#if HOST_DEBUG - printf(" test[%d] : %3.2f\n", i, test[i]); - printf(" corr[%d] : %3.2f\n", i, correct[i]); -#endif - // tell us which index fails + 2 - // (so that if i==0,i==1 fails, we don't - // think it was a 'not-finished yet' or pass) -// return i+10; - return 2; - } - } - return 1; -} - -void finishTest( int correct, long long num_cycles, long long num_retired ) -{ - int toHostValue = correct; -#if HOST_DEBUG - if ( toHostValue == 1 ) - printf( "*** PASSED ***\n" ); - else - printf( "*** FAILED *** (tohost = %d)\n", toHostValue ); - exit(0); -#else - // we no longer run in -testrun mode, which means we can't use - // the tohost register to communicate "test is done" and "test results" - // so instead we will communicate through print* functions! - if ( correct == 1 ) - { - printstr( "*** PASSED *** (num_cycles = 0x" ); - printhex(num_cycles); - printstr( ", num_inst_retired = 0x"); - printhex(num_retired); - printstr( ")\n" ); - } - else - { - printstr( "*** FAILED *** (num_cycles = 0x"); - printhex(num_cycles); - printstr( ", num_inst_retired = 0x"); - printhex(num_retired); - printstr( ")\n" ); - } - exit(); -#endif -} - - -// deprecated - cr10/stats-enable register no longer exists -void setStats( int enable ) -{ -#if ( !HOST_DEBUG && SET_STATS ) - asm( "mtpcr %0, cr10" : : "r" (enable) ); -#endif -} - -long long getCycles() -{ - long long cycles = 1337; -#if ( !HOST_DEBUG && SET_STATS ) - __asm__ __volatile__( "rdcycle %0" : "=r" (cycles) ); -#endif - return cycles; -} - -long long getInstRetired() -{ - long long inst_retired = 1338; -#if ( !HOST_DEBUG && SET_STATS ) - __asm__ __volatile__( "rdinstret %0" : "=r" (inst_retired) ); -#endif - return inst_retired; -} - -//-------------------------------------------------------------------------- -// vvadd function - -// scalar C implementation -void vvadd( int n, float a[], float b[], float c[] ) -{ - int i; - for ( i = 0; i < n; i++ ) - c[i] = a[i] + b[i]; -} - -// assembly implementations can be found in *_asm.S - -//-------------------------------------------------------------------------- -// Main - -int main( int argc, char* argv[] ) -{ - float results_data[DATA_SIZE]; - long long start_cycles = 0; - long long stop_cycles = 0; - long long num_cycles; - long long start_retired = 0; - long long stop_retired = 0; - long long num_retired; - - // Output the input array - -#if HOST_DEBUG - printArray( "input1", DATA_SIZE, input1_data ); - printArray( "input2", DATA_SIZE, input2_data ); - printArray( "verify", DATA_SIZE, verify_data ); -#endif - - // -------------------------------------------------- - // If needed we preallocate everything in the caches - -#if PREALLOCATE - -#ifdef SCALAR_C - vvadd( DATA_SIZE, input1_data, input2_data, results_data ); -#else -#ifdef SCALAR_ASM - scalar_vvadd_asm( DATA_SIZE, input1_data, input2_data, results_data ); -#else -#ifdef VT_ASM - vt_vvadd_asm( DATA_SIZE, input1_data, input2_data, results_data ); -#endif -#endif -#endif - -#endif - - // -------------------------------------------------- - // Do the vvadd - start_cycles = getCycles(); - start_retired = getInstRetired(); - -#ifdef SCALAR_C - vvadd( DATA_SIZE, input1_data, input2_data, results_data ); -#else -#ifdef SCALAR_ASM - #if HOST_DEBUG==0 - scalar_vvadd_asm( DATA_SIZE, input1_data, input2_data, results_data ); - #endif -#else -#ifdef VT_ASM - #if HOST_DEBUG==0 - vt_vvadd_asm( DATA_SIZE, input1_data, input2_data, results_data ); - #endif -#endif -#endif -#endif - - stop_cycles = getCycles(); - stop_retired = getInstRetired(); - num_cycles = stop_cycles - start_cycles; - num_retired = stop_retired - start_retired; - -// printstr("stop_cycles: "); printhex(stop_cycles); printstr("\n"); -// printstr("star_cycles: "); printhex(start_cycles); printstr("\n"); - - // -------------------------------------------------- - // Print out the results - -#if HOST_DEBUG - printArray( "results", DATA_SIZE, results_data ); -#endif - - // -------------------------------------------------- - // Check the results - int correct = verify( DATA_SIZE, results_data, verify_data ); - finishTest(correct, num_cycles, num_retired); -} diff --git a/benchmarks/vec-vvadd/vvadd_gendata.pl b/benchmarks/vec-vvadd/vvadd_gendata.pl deleted file mode 100755 index 10fc4e9..0000000 --- a/benchmarks/vec-vvadd/vvadd_gendata.pl +++ /dev/null @@ -1,139 +0,0 @@ -#!/usr/bin/perl -w -#========================================================================== -# vvadd_gendata.pl -# -# Author : Christopher Batten (cbatten@mit.edu) -# Date : April 29, 2005 -# -(our $usageMsg = <<'ENDMSG') =~ s/^\#//gm; -# -# Simple script which creates an input data set and the reference data -# for the vvadd benchmark. -# -ENDMSG - -use strict "vars"; -use warnings; -no warnings("once"); -use Getopt::Long; - -#-------------------------------------------------------------------------- -# Command line processing -#-------------------------------------------------------------------------- - -our %opts; - -sub usage() -{ - - print "\n"; - print " Usage: vvadd_gendata.pl [options] \n"; - print "\n"; - print " Options:\n"; - print " --help print this message\n"; - print " --size size of input data [1000]\n"; - print " --seed random seed [1]\n"; - print "$usageMsg"; - - exit(); -} - -sub processCommandLine() -{ - - $opts{"help"} = 0; - $opts{"size"} = 1000; - $opts{"seed"} = 1; - Getopt::Long::GetOptions( \%opts, 'help|?', 'size:i', 'seed:i' ) or usage(); - $opts{"help"} and usage(); - -} - -#-------------------------------------------------------------------------- -# Helper Functions -#-------------------------------------------------------------------------- - -sub printArray -{ - my $arrayName = $_[0]; - my $arrayRef = $_[1]; - - my $numCols = 20; - my $arrayLen = scalar(@{$arrayRef}); - - print "float ".$arrayName."[DATA_SIZE] = \n"; - print "{\n"; - - if ( $arrayLen <= $numCols ) { - print " "; - for ( my $i = 0; $i < $arrayLen; $i++ ) { - print sprintf("%3.2f",$arrayRef->[$i]); - if ( $i != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - else { - my $numRows = int($arrayLen/$numCols); - for ( my $j = 0; $j < $numRows; $j++ ) { - print " "; - for ( my $i = 0; $i < $numCols; $i++ ) { - my $index = $j*$numCols + $i; - print sprintf("%3.2f",$arrayRef->[$index]); - if ( $index != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - if ( $arrayLen > ($numRows*$numCols) ) { - print " "; - for ( my $i = 0; $i < ($arrayLen-($numRows*$numCols)); $i++ ) { - my $index = $numCols*$numRows + $i; - print sprintf("%3.2f",$arrayRef->[$index]); - if ( $index != $arrayLen-1 ) { - print ", "; - } - } - print "\n"; - } - - } - - print "};\n\n"; -} - -#-------------------------------------------------------------------------- -# Main -#-------------------------------------------------------------------------- - -sub main() -{ - - processCommandLine(); - srand($opts{"seed"}); - - my @values1; - my @values2; - my @sum; - for ( my $i = 0; $i < $opts{"size"}; $i++ ) { - my $value1 = (rand(999)); - my $value2 = (rand(999)); - push( @values1, $value1 ); - push( @values2, $value2 ); - push( @sum, $value1 + $value2 ); - } - - - print "\n\#define DATA_SIZE ".$opts{"size"}." \n\n"; - printArray( "input1_data", \@values1 ); - printArray( "input2_data", \@values2 ); - printArray( "verify_data", \@sum ); - -} - -main(); - diff --git a/env b/env index cdf86f5..0bf56e2 160000 --- a/env +++ b/env @@ -1 +1 @@ -Subproject commit cdf86f59e5706d1c35371b555892fe7b8ab2b01d +Subproject commit 0bf56e2156ad5393ec2997e4f3dfba98778e8f1f diff --git a/isa/Makefile b/isa/Makefile index 3a8b265..07aef50 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -6,9 +6,7 @@ isa_src_dir := . include $(isa_src_dir)/rv64ui/Makefrag include $(isa_src_dir)/rv64uf/Makefrag -include $(isa_src_dir)/rv64uv/Makefrag include $(isa_src_dir)/rv64si/Makefrag -include $(isa_src_dir)/rv64sv/Makefrag include $(isa_src_dir)/rv64mi/Makefrag include $(isa_src_dir)/rv32ui/Makefrag include $(isa_src_dir)/rv32si/Makefrag @@ -23,9 +21,9 @@ default: all RISCV_PREFIX=riscv64-unknown-elf- RISCV_GCC = $(RISCV_PREFIX)gcc ENTROPY = -DENTROPY=$(shell echo $$$$) -RISCV_GCC_OPTS = $(ENTROPY) -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -Wa,-march=RVIMAFDXhwacha +RISCV_GCC_OPTS = $(ENTROPY) -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles RISCV_OBJDUMP = $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data -RISCV_SIM = spike --extension=hwacha +RISCV_SIM = spike vpath %.S $(isa_src_dir) @@ -62,18 +60,6 @@ $$($(1)_v_tests): $(1)-v-%: $(1)/%.S $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -std=gnu99 -O2 -I$(isa_src_dir)/../env/v -I$(isa_src_dir)/macros/scalar -T$(isa_src_dir)/../env/v/link.ld $(isa_src_dir)/../env/v/entry.S $(isa_src_dir)/../env/v/vm.c $$< -lc -o $$@ $(1)_tests += $$($(1)_v_tests) -$$($(1)_p_vec_tests): $(1)-p-vec-%: $(1)/%.S - $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(isa_src_dir)/../env/p -I$(isa_src_dir)/macros/vector -T$(isa_src_dir)/../env/p/link.ld $$< -o $$@ -$(1)_tests += $$($(1)_p_vec_tests) - -$$($(1)_pt_vec_tests): $(1)-pt-vec-%: $(1)/%.S - $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(isa_src_dir)/../env/pt -I$(isa_src_dir)/macros/vector -T$(isa_src_dir)/../env/pt/link.ld $$< -o $$@ -$(1)_tests += $$($(1)_pt_vec_tests) - -$$($(1)_v_vec_tests): $(1)-v-vec-%: $(1)/%.S - $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -std=gnu99 -O2 -I$(isa_src_dir)/../env/v -I$(isa_src_dir)/macros/vector -T$(isa_src_dir)/../env/v/link.ld $(isa_src_dir)/../env/v/entry.S $(isa_src_dir)/../env/v/vm.c $$< -lc -o $$@ -$(1)_tests += $$($(1)_v_vec_tests) - $(1)_tests_dump = $$(addsuffix .dump, $$($(1)_tests)) $(1)_tests_hex = $$(addsuffix .hex, $$($(1)_tests)) @@ -90,9 +76,7 @@ $(eval $(call compile_template,rv32si,-m32)) $(eval $(call compile_template,rv32mi,-m32)) $(eval $(call compile_template,rv64ui)) $(eval $(call compile_template,rv64uf)) -$(eval $(call compile_template,rv64uv)) $(eval $(call compile_template,rv64si)) -$(eval $(call compile_template,rv64sv)) $(eval $(call compile_template,rv64mi)) tests_dump = $(addsuffix .dump, $(tests)) diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h index 6242f0b..48ce028 100644 --- a/isa/macros/scalar/test_macros.h +++ b/isa/macros/scalar/test_macros.h @@ -564,129 +564,6 @@ test_ ## testnum: \ .double result; \ 1: - -#----------------------------------------------------------------------- -# RV64SV MACROS -#----------------------------------------------------------------------- - -#define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \ - la a0, handler ## testnum; \ - csrw stvec, a0; \ - vsetcfg nxreg, nfreg; \ - li a0, 4; \ - vsetvl a0, a0; \ - la a0, src1; \ - la a1, src2; \ - vld vx2, a0; \ - vld vx3, a1; \ - lui a0,%hi(vtcode1 ## testnum); \ - vf %lo(vtcode1 ## testnum)(a0); \ - la reg2, dest; \ -illegal ## testnum: \ - inst reg1, reg2; \ - la a3, dest; \ - vsd vx2, a3; \ - fence; \ -vtcode1 ## testnum: \ - add x2, x2, x3; \ - stop; \ -vtcode2 ## testnum: \ - add x2, x2, x3; \ - stop; \ -handler ## testnum: \ - vxcptkill; \ - li TESTNUM,2; \ - csrr a0, scause; \ - li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \ - bne a0,a1,fail; \ - csrr a0, sbadaddr; \ - la a1, illegal ## testnum; \ - lw a2, 0(a1); \ - bne a0, a2, fail; \ - vsetcfg 32,0; \ - li a0,4; \ - vsetvl a0,a0; \ - la a0,src1; \ - la a1,src2; \ - vld vx2,a0; \ - vld vx3,a1; \ - lui a0,%hi(vtcode2 ## testnum); \ - vf %lo(vtcode2 ## testnum)(a0); \ - la a3,dest; \ - vsd vx2,a3; \ - fence; \ - ld a1,0(a3); \ - li a2,5; \ - li TESTNUM,2; \ - bne a1,a2,fail; \ - ld a1,8(a3); \ - li TESTNUM,3; \ - bne a1,a2,fail; \ - ld a1,16(a3); \ - li TESTNUM,4; \ - bne a1,a2,fail; \ - ld a1,24(a3); \ - li TESTNUM,5; \ - bne a1,a2,fail; \ - -#define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \ - la a0, handler ## testnum; \ - csrw stvec, a0; \ - vsetcfg nxreg, nfreg; \ - li a0, 4; \ - vsetvl a0, a0; \ - la a0, src1; \ - la a1, src2; \ - vld vx2, a0; \ - vld vx3, a1; \ - lui a0,%hi(vtcode1 ## testnum); \ - vf %lo(vtcode1 ## testnum)(a0); \ - la a3, dest; \ - vsd vx2, a3; \ - fence; \ -vtcode1 ## testnum: \ - add x2, x2, x3; \ -illegal ## testnum: \ - inst reg1, reg2, reg3; \ - stop; \ -vtcode2 ## testnum: \ - add x2, x2, x3; \ - stop; \ -handler ## testnum: \ - vxcptkill; \ - li TESTNUM,2; \ - csrr a0, scause; \ - li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \ - bne a0,a1,fail; \ - csrr a0, sbadaddr; \ - la a1,illegal ## testnum; \ - bne a0,a1,fail; \ - vsetcfg 32,0; \ - li a0,4; \ - vsetvl a0,a0; \ - la a0,src1; \ - la a1,src2; \ - vld vx2,a0; \ - vld vx3,a1; \ - lui a0,%hi(vtcode2 ## testnum); \ - vf %lo(vtcode2 ## testnum)(a0); \ - la a3,dest; \ - vsd vx2,a3; \ - fence; \ - ld a1,0(a3); \ - li a2,5; \ - li TESTNUM,2; \ - bne a1,a2,fail; \ - ld a1,8(a3); \ - li TESTNUM,3; \ - bne a1,a2,fail; \ - ld a1,16(a3); \ - li TESTNUM,4; \ - bne a1,a2,fail; \ - ld a1,24(a3); \ - li TESTNUM,5; \ - bne a1,a2,fail; \ - #----------------------------------------------------------------------- # Pass and fail code (assumes test num is in TESTNUM) #----------------------------------------------------------------------- diff --git a/isa/rv64sv/Makefrag b/isa/rv64sv/Makefrag deleted file mode 100644 index 9a2746c..0000000 --- a/isa/rv64sv/Makefrag +++ /dev/null @@ -1,14 +0,0 @@ -#======================================================================= -# Makefrag for rv64sv tests -#----------------------------------------------------------------------- - -rv64sv_sc_tests = \ - illegal_cfg_nxpr illegal_cfg_nfpr illegal_inst privileged_inst \ - illegal_tvec_regid \ - illegal_vt_inst illegal_vt_regid \ - ma_utld ma_utsd ma_vld ma_vsd \ - ma_vt_inst \ - -rv64sv_p_tests = $(addprefix rv64sv-p-, $(rv64sv_sc_tests)) - -spike_tests += $(rv64sv_p_tests) diff --git a/isa/rv64sv/illegal_cfg_nfpr.S b/isa/rv64sv/illegal_cfg_nfpr.S deleted file mode 100644 index be114cc..0000000 --- a/isa/rv64sv/illegal_cfg_nfpr.S +++ /dev/null @@ -1,93 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# illegal_tvec_cmd.S -#----------------------------------------------------------------------------- -# -# Test illegal tvec command trap. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64SV -RVTEST_CODE_BEGIN - - li a0,33 - slli a0,a0,6 - vsetcfg a0 - -vtcode2: - add x2,x2,x3 - stop - -stvec_handler: - vxcptkill - - li TESTNUM,2 - - # check cause - csrr a3, scause - li a4,HWACHA_CAUSE_ILLEGAL_CFG - bne a3,a4,fail - - # check vec irq aux - csrr a3, sbadaddr - li a4, 1 - bne a3,a4,fail - - # make sure vector unit has cleared out - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - la a3,src1 - la a4,src2 - vld vx2,a3 - vld vx3,a4 - lui a0,%hi(vtcode2) - vf %lo(vtcode2)(a0) - la a5,dest - vsd vx2,a5 - fence - - ld a1,0(a5) - li a2,5 - li TESTNUM,2 - bne a1,a2,fail - ld a1,8(a5) - li TESTNUM,3 - bne a1,a2,fail - ld a1,16(a5) - li TESTNUM,4 - bne a1,a2,fail - ld a1,24(a5) - li TESTNUM,5 - bne a1,a2,fail - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .dword 1 - .dword 2 - .dword 3 - .dword 4 -src2: - .dword 4 - .dword 3 - .dword 2 - .dword 1 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - -RVTEST_DATA_END diff --git a/isa/rv64sv/illegal_cfg_nxpr.S b/isa/rv64sv/illegal_cfg_nxpr.S deleted file mode 100644 index 51cc84a..0000000 --- a/isa/rv64sv/illegal_cfg_nxpr.S +++ /dev/null @@ -1,92 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# illegal_tvec_cmd.S -#----------------------------------------------------------------------------- -# -# Test illegal tvec command trap. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64SV -RVTEST_CODE_BEGIN - - li a0,33 - vsetcfg a0 - -vtcode2: - add x2,x2,x3 - stop - -stvec_handler: - vxcptkill - - li TESTNUM,2 - - # check cause - csrr a3, scause - li a4,HWACHA_CAUSE_ILLEGAL_CFG - bne a3,a4,fail - - # check vec irq aux - csrr a3, sbadaddr - li a4, 0 - bne a3,a4,fail - - # make sure vector unit has cleared out - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - la a3,src1 - la a4,src2 - vld vx2,a3 - vld vx3,a4 - lui a0,%hi(vtcode2) - vf %lo(vtcode2)(a0) - la a5,dest - vsd vx2,a5 - fence - - ld a1,0(a5) - li a2,5 - li TESTNUM,2 - bne a1,a2,fail - ld a1,8(a5) - li TESTNUM,3 - bne a1,a2,fail - ld a1,16(a5) - li TESTNUM,4 - bne a1,a2,fail - ld a1,24(a5) - li TESTNUM,5 - bne a1,a2,fail - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .dword 1 - .dword 2 - .dword 3 - .dword 4 -src2: - .dword 4 - .dword 3 - .dword 2 - .dword 1 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - -RVTEST_DATA_END diff --git a/isa/rv64sv/illegal_inst.S b/isa/rv64sv/illegal_inst.S deleted file mode 100644 index 7e653d1..0000000 --- a/isa/rv64sv/illegal_inst.S +++ /dev/null @@ -1,99 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# illegal_tvec_cmd.S -#----------------------------------------------------------------------------- -# -# Test illegal tvec command trap. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64SV -RVTEST_CODE_BEGIN - - .word 0xff00002b - - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - -vtcode1: - lw x2, 0(x1) - stop - -vtcode2: - add x2,x2,x3 - stop - -stvec_handler: - vxcptkill - - li TESTNUM,2 - - # check cause - csrr a3, scause - li a4,HWACHA_CAUSE_ILLEGAL_INSTRUCTION - bne a3,a4,fail - - # check vec irq aux - csrr a3, sbadaddr - li a4, 0xff00002b - bne a3,a4,fail - - # make sure vector unit has cleared out - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - la a3,src1 - la a4,src2 - vld vx2,a3 - vld vx3,a4 - lui a0,%hi(vtcode2) - vf %lo(vtcode2)(a0) - la a5,dest - vsd vx2,a5 - fence - - ld a1,0(a5) - li a2,5 - li TESTNUM,2 - bne a1,a2,fail - ld a1,8(a5) - li TESTNUM,3 - bne a1,a2,fail - ld a1,16(a5) - li TESTNUM,4 - bne a1,a2,fail - ld a1,24(a5) - li TESTNUM,5 - bne a1,a2,fail - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .dword 1 - .dword 2 - .dword 3 - .dword 4 -src2: - .dword 4 - .dword 3 - .dword 2 - .dword 1 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - -RVTEST_DATA_END diff --git a/isa/rv64sv/illegal_tvec_regid.S b/isa/rv64sv/illegal_tvec_regid.S deleted file mode 100644 index 30403ba..0000000 --- a/isa/rv64sv/illegal_tvec_regid.S +++ /dev/null @@ -1,51 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# illegal_tvec_regid.S -#----------------------------------------------------------------------------- -# -# Test illegal tvec regid trap. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64SV -RVTEST_CODE_BEGIN - - TEST_ILLEGAL_TVEC_REGID(2, 5, 5, vsd, vx7, a2) - TEST_ILLEGAL_TVEC_REGID(3, 5, 5, vld, vx7, a2) - - TEST_ILLEGAL_TVEC_REGID(4, 5, 5, vfsd, vf7, a2) - TEST_ILLEGAL_TVEC_REGID(5, 5, 5, vfld, vf7, a2) - - TEST_PASSFAIL - -# the handler gets rewritten for every test, but need this for the framework -stvec_handler: - j fail - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .dword 1 - .dword 2 - .dword 3 - .dword 4 -src2: - .dword 4 - .dword 3 - .dword 2 - .dword 1 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - -RVTEST_DATA_END diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S deleted file mode 100644 index 080cd2f..0000000 --- a/isa/rv64sv/illegal_vt_inst.S +++ /dev/null @@ -1,107 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# illegal_vt_inst.S -#----------------------------------------------------------------------------- -# -# Test illegal vt instruction trap. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64SV -RVTEST_CODE_BEGIN - - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - la a3,src1 - la a4,src2 - vld vx2,a3 - vld vx3,a4 - lui a0,%hi(vtcode1) - vf %lo(vtcode1)(a0) - fence - -vtcode1: - add x2,x2,x3 -illegal: - .word 0x0 - stop - -vtcode2: - add x2,x2,x3 - stop - -stvec_handler: - vxcptkill - - li TESTNUM,2 - - # check cause - csrr a3, scause - li a4,HWACHA_CAUSE_VF_ILLEGAL_INSTRUCTION - bne a3,a4,fail - - # check badvaddr - csrr a3, sbadaddr - la a4,illegal - bne a3,a4,fail - - # make sure vector unit has cleared out - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - la a3,src1 - la a4,src2 - vld vx2,a3 - vld vx3,a4 - lui a0,%hi(vtcode2) - vf %lo(vtcode2)(a0) - la a5,dest - vsd vx2,a5 - fence - - ld a1,0(a5) - li a2,5 - li TESTNUM,2 - bne a1,a2,fail - ld a1,8(a5) - li TESTNUM,3 - bne a1,a2,fail - ld a1,16(a5) - li TESTNUM,4 - bne a1,a2,fail - ld a1,24(a5) - li TESTNUM,5 - bne a1,a2,fail - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .dword 1 - .dword 2 - .dword 3 - .dword 4 -src2: - .dword 4 - .dword 3 - .dword 2 - .dword 1 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - -RVTEST_DATA_END diff --git a/isa/rv64sv/illegal_vt_regid.S b/isa/rv64sv/illegal_vt_regid.S deleted file mode 100644 index e74b614..0000000 --- a/isa/rv64sv/illegal_vt_regid.S +++ /dev/null @@ -1,53 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# xcpt_illegal_vt_regid.S -#----------------------------------------------------------------------------- -# -# Test illegal vt regid trap. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64SV -RVTEST_CODE_BEGIN - - TEST_ILLEGAL_VT_REGID(2, 5, 5, add, x7, x1, x2) - TEST_ILLEGAL_VT_REGID(3, 5, 5, add, x1, x7, x2) - TEST_ILLEGAL_VT_REGID(4, 5, 5, add, x1, x2, x7) - - TEST_ILLEGAL_VT_REGID(5, 5, 5, fadd.d, f7, f1, f2) - TEST_ILLEGAL_VT_REGID(6, 5, 5, fadd.d, f1, f7, f2) - TEST_ILLEGAL_VT_REGID(7, 5, 5, fadd.d, f1, f2, f7) - - TEST_PASSFAIL - -# the handler gets rewritten for every test, but need this for the framework -stvec_handler: - j fail - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .dword 1 - .dword 2 - .dword 3 - .dword 4 -src2: - .dword 4 - .dword 3 - .dword 2 - .dword 1 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - -RVTEST_DATA_END diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S deleted file mode 100644 index 5ea6ee6..0000000 --- a/isa/rv64sv/ma_utld.S +++ /dev/null @@ -1,103 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# ma_utld.S -#----------------------------------------------------------------------------- -# -# Test misaligned ut ld trap. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64SV -RVTEST_CODE_BEGIN - - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - la a3, dest+1 - vmsv vx1, a3 - lui a0,%hi(vtcode1) - vf %lo(vtcode1)(a0) - fence - -vtcode1: - lw x2, 0(x1) - stop - -vtcode2: - add x2,x2,x3 - stop - -stvec_handler: - vxcptkill - - li TESTNUM,2 - - # check cause - csrr a3, scause - li a4,HWACHA_CAUSE_MISALIGNED_LOAD - bne a3,a4,fail - - # check vec irq aux - csrr a3, sbadaddr - la a4,dest+1 - bne a3,a4,fail - - # make sure vector unit has cleared out - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - la a3,src1 - la a4,src2 - vld vx2,a3 - vld vx3,a4 - lui a0,%hi(vtcode2) - vf %lo(vtcode2)(a0) - la a5,dest - vsd vx2,a5 - fence - - ld a1,0(a5) - li a2,5 - li TESTNUM,2 - bne a1,a2,fail - ld a1,8(a5) - li TESTNUM,3 - bne a1,a2,fail - ld a1,16(a5) - li TESTNUM,4 - bne a1,a2,fail - ld a1,24(a5) - li TESTNUM,5 - bne a1,a2,fail - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .dword 1 - .dword 2 - .dword 3 - .dword 4 -src2: - .dword 4 - .dword 3 - .dword 2 - .dword 1 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - -RVTEST_DATA_END diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S deleted file mode 100644 index 47df11b..0000000 --- a/isa/rv64sv/ma_utsd.S +++ /dev/null @@ -1,105 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# ma_utsd.S -#----------------------------------------------------------------------------- -# -# Test misaligned ut sd trap. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64SV -RVTEST_CODE_BEGIN - - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - la a3, dest+1 - vmsv vx1, a3 - lui a0,%hi(vtcode1) - vf %lo(vtcode1)(a0) - la a3, dest+1 - vsd vx1, a3 - fence - -vtcode1: - sw x2, 0(x1) - stop - -vtcode2: - add x2,x2,x3 - stop - -stvec_handler: - vxcptkill - - li TESTNUM,2 - - # check cause - csrr a3, scause - li a4,HWACHA_CAUSE_MISALIGNED_STORE - bne a3,a4,fail - - # check vec irq aux - csrr a3, sbadaddr - la a4, dest+1 - bne a3,a4,fail - - # make sure vector unit has cleared out - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - la a3,src1 - la a4,src2 - vld vx2,a3 - vld vx3,a4 - lui a0,%hi(vtcode2) - vf %lo(vtcode2)(a0) - la a5,dest - vsd vx2,a5 - fence - - ld a1,0(a5) - li a2,5 - li TESTNUM,2 - bne a1,a2,fail - ld a1,8(a5) - li TESTNUM,3 - bne a1,a2,fail - ld a1,16(a5) - li TESTNUM,4 - bne a1,a2,fail - ld a1,24(a5) - li TESTNUM,5 - bne a1,a2,fail - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .dword 1 - .dword 2 - .dword 3 - .dword 4 -src2: - .dword 4 - .dword 3 - .dword 2 - .dword 1 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - -RVTEST_DATA_END diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S deleted file mode 100644 index 2cdc2d4..0000000 --- a/isa/rv64sv/ma_vld.S +++ /dev/null @@ -1,104 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# ma_vld.S -#----------------------------------------------------------------------------- -# -# Test misaligned vector ld trap. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64SV -RVTEST_CODE_BEGIN - - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - la a3, dest+1 - vld vx2,a3 - vld vx3,a4 - lui a0,%hi(vtcode1) - vf %lo(vtcode1)(a0) - fence - -vtcode1: - add x2,x2,x3 - stop - -vtcode2: - add x2,x2,x3 - stop - -stvec_handler: - vxcptkill - - li TESTNUM,2 - - # check cause - csrr a3, scause - li a4,HWACHA_CAUSE_MISALIGNED_LOAD - bne a3,a4,fail - - # check vec irq aux - csrr a3, sbadaddr - la a4,dest+1 - bne a3,a4,fail - - # make sure vector unit has cleared out - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - la a3,src1 - la a4,src2 - vld vx2,a3 - vld vx3,a4 - lui a0,%hi(vtcode2) - vf %lo(vtcode2)(a0) - la a5,dest - vsd vx2,a5 - fence - - ld a1,0(a5) - li a2,5 - li TESTNUM,2 - bne a1,a2,fail - ld a1,8(a5) - li TESTNUM,3 - bne a1,a2,fail - ld a1,16(a5) - li TESTNUM,4 - bne a1,a2,fail - ld a1,24(a5) - li TESTNUM,5 - bne a1,a2,fail - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .dword 1 - .dword 2 - .dword 3 - .dword 4 -src2: - .dword 4 - .dword 3 - .dword 2 - .dword 1 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - -RVTEST_DATA_END diff --git a/isa/rv64sv/ma_vsd.S b/isa/rv64sv/ma_vsd.S deleted file mode 100644 index e113f99..0000000 --- a/isa/rv64sv/ma_vsd.S +++ /dev/null @@ -1,107 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# ma_vsd.S -#----------------------------------------------------------------------------- -# -# Test misaligned vector sd trap. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64SV -RVTEST_CODE_BEGIN - - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - la a3, src1 - la a4, src2 - vld vx2,a3 - vld vx3,a4 - lui a0,%hi(vtcode1) - vf %lo(vtcode1)(a0) - la a3, dest+1 - vsd vx1, a3 - fence - -vtcode1: - add x2,x2,x3 - stop - -vtcode2: - add x2,x2,x3 - stop - -stvec_handler: - vxcptkill - - li TESTNUM,2 - - # check cause - csrr a3, scause - li a4,HWACHA_CAUSE_MISALIGNED_STORE - bne a3,a4,fail - - # check vec irq aux - csrr a3, sbadaddr - la a4,dest+1 - bne a3,a4,fail - - # make sure vector unit has cleared out - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - la a3,src1 - la a4,src2 - vld vx2,a3 - vld vx3,a4 - lui a0,%hi(vtcode2) - vf %lo(vtcode2)(a0) - la a5,dest - vsd vx2,a5 - fence - - ld a1,0(a5) - li a2,5 - li TESTNUM,2 - bne a1,a2,fail - ld a1,8(a5) - li TESTNUM,3 - bne a1,a2,fail - ld a1,16(a5) - li TESTNUM,4 - bne a1,a2,fail - ld a1,24(a5) - li TESTNUM,5 - bne a1,a2,fail - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .dword 1 - .dword 2 - .dword 3 - .dword 4 -src2: - .dword 4 - .dword 3 - .dword 2 - .dword 1 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - -RVTEST_DATA_END diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S deleted file mode 100644 index a257942..0000000 --- a/isa/rv64sv/ma_vt_inst.S +++ /dev/null @@ -1,99 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# ma_vt_inst.S -#----------------------------------------------------------------------------- -# -# Test misaligned vt instruction trap. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64SV -RVTEST_CODE_BEGIN - - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - lui a0,%hi(vtcode1+2) - vf %lo(vtcode1+2)(a0) -1: j 1b - -vtcode1: - add x2,x2,x3 - stop - -stvec_handler: - vxcptkill - - li TESTNUM,2 - - # check cause - csrr a3, scause - li a4,HWACHA_CAUSE_VF_MISALIGNED_FETCH - bne a3,a4,fail - - # check badvaddr - csrr a3, sbadaddr - la a4,vtcode1+2 - andi a3, a3, -4 # mask off lower bits so that may - andi a4, a4, -4 # ignore impl. specific behavior - bne a3,a4,fail - - # make sure vector unit has cleared out - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - la a3,src1 - la a4,src2 - vld vx2,a3 - vld vx3,a4 - lui a0,%hi(vtcode1) - vf %lo(vtcode1)(a0) - la a5,dest - vsd vx2,a5 - fence - - ld a1,0(a5) - li a2,5 - li TESTNUM,2 - bne a1,a2,fail - ld a1,8(a5) - li TESTNUM,3 - bne a1,a2,fail - ld a1,16(a5) - li TESTNUM,4 - bne a1,a2,fail - ld a1,24(a5) - li TESTNUM,5 - bne a1,a2,fail - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .dword 1 - .dword 2 - .dword 3 - .dword 4 -src2: - .dword 4 - .dword 3 - .dword 2 - .dword 1 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - -RVTEST_DATA_END diff --git a/isa/rv64sv/privileged_inst.S b/isa/rv64sv/privileged_inst.S deleted file mode 100644 index e59d361..0000000 --- a/isa/rv64sv/privileged_inst.S +++ /dev/null @@ -1,100 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# illegal_tvec_cmd.S -#----------------------------------------------------------------------------- -# -# Test illegal tvec command trap. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64SV -RVTEST_CODE_BEGIN - - li a3, SSTATUS_PS - csrc sstatus, a3 - la t0, 1f - csrw sepc, t0 - sret -1: - -privileged_inst: - vxcptcause a3 # privileged inst - -vtcode2: - add x2,x2,x3 - stop - -stvec_handler: - vxcptkill - - li TESTNUM,2 - - # check cause - csrr a3, scause - li a4,HWACHA_CAUSE_PRIVILEGED_INSTRUCTION - bne a3,a4,fail - - # check vec irq aux - csrr a3, sbadaddr - la a4, privileged_inst - lw a5, 0(a4) - bne a3,a5,fail - - # make sure vector unit has cleared out - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - la a3,src1 - la a4,src2 - vld vx2,a3 - vld vx3,a4 - lui a0,%hi(vtcode2) - vf %lo(vtcode2)(a0) - la a5,dest - vsd vx2,a5 - fence - - ld a1,0(a5) - li a2,5 - li TESTNUM,2 - bne a1,a2,fail - ld a1,8(a5) - li TESTNUM,3 - bne a1,a2,fail - ld a1,16(a5) - li TESTNUM,4 - bne a1,a2,fail - ld a1,24(a5) - li TESTNUM,5 - bne a1,a2,fail - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .dword 1 - .dword 2 - .dword 3 - .dword 4 -src2: - .dword 4 - .dword 3 - .dword 2 - .dword 1 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - -RVTEST_DATA_END diff --git a/isa/rv64uf/Makefrag b/isa/rv64uf/Makefrag index d604a85..c42b5f7 100644 --- a/isa/rv64uf/Makefrag +++ b/isa/rv64uf/Makefrag @@ -6,14 +6,8 @@ rv64uf_sc_tests = \ fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin fsgnj \ ldst move structural recoding \ -rv64uf_sc_vec_tests = \ - fadd fcmp fcvt fcvt_w fmadd fmin fsgnj \ - rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sc_tests)) rv64uf_pt_tests = $(addprefix rv64uf-pt-, $(rv64uf_sc_tests)) rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sc_tests)) -rv64uf_p_vec_tests = $(addprefix rv64uf-p-vec-, $(rv64uf_sc_vec_tests)) -rv64uf_pt_vec_tests = $(addprefix rv64uf-pt-vec-, $(rv64uf_sc_vec_tests)) -rv64uf_v_vec_tests = $(addprefix rv64uf-v-vec-, $(rv64uf_sc_vec_tests)) -spike_tests += $(rv64uf_p_tests) $(rv64uf_pt_tests) $(rv64uf_v_tests) $(rv64uf_p_vec_tests) $(rv64uf_pt_vec_tests) $(rv64uf_v_vec_tests) +spike_tests += $(rv64uf_p_tests) $(rv64uf_pt_tests) $(rv64uf_v_tests) diff --git a/isa/rv64ui/Makefrag b/isa/rv64ui/Makefrag index 53f9a7f..d8d21af 100644 --- a/isa/rv64ui/Makefrag +++ b/isa/rv64ui/Makefrag @@ -29,25 +29,9 @@ rv64ui_sc_tests = \ rv64ui_mc_tests = \ lrsc -rv64ui_sc_vec_tests = \ - add addi addiw addw \ - and andi \ - lui \ - mul mulh mulhsu mulhu mulw \ - or ori \ - sll slli slliw sllw \ - slt slti sltiu sltu \ - sra srai sraiw sraw \ - srl srli srliw srlw \ - sub subw \ - xor xori \ - rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sc_tests)) rv64ui_pt_tests = $(addprefix rv64ui-pt-, $(rv64ui_sc_tests)) rv64ui_pm_tests = $(addprefix rv64ui-pm-, $(rv64ui_mc_tests)) rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sc_tests)) -rv64ui_p_vec_tests = $(addprefix rv64ui-p-vec-, $(rv64ui_sc_vec_tests)) -rv64ui_pt_vec_tests = $(addprefix rv64ui-pt-vec-, $(rv64ui_sc_vec_tests)) -rv64ui_v_vec_tests = $(addprefix rv64ui-v-vec-, $(rv64ui_sc_vec_tests)) -spike_tests += $(rv64ui_p_tests) $(rv64ui_pm_tests) $(rv64ui_pt_tests) $(rv64ui_v_tests) $(rv64ui_p_vec_tests) $(rv64ui_pt_vec_tests) $(rv64ui_v_vec_tests) +spike_tests += $(rv64ui_p_tests) $(rv64ui_pm_tests) $(rv64ui_pt_tests) $(rv64ui_v_tests) diff --git a/isa/rv64uv/Makefrag b/isa/rv64uv/Makefrag deleted file mode 100644 index 856721b..0000000 --- a/isa/rv64uv/Makefrag +++ /dev/null @@ -1,34 +0,0 @@ -#======================================================================= -# Makefrag for rv64uv tests -#----------------------------------------------------------------------- - -rv64uv_sc_tests = \ - wakeup fence \ - vsetcfgi vsetcfg vsetvl keepcfg \ - vmvv vmsv \ - vfmvv vfmsv_d vfmsv_s \ - utidx \ - lb lbu lh lhu lw lwu ld \ - sb sh sw sd \ - fld flw \ - fsd fsw \ - amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoswap_d amoxor_d \ - amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoswap_w amoxor_w \ - imul \ - movn movz \ - fcvt fma fma_many \ - fmovn fmovz \ - vvadd_d vvadd_w vvadd_fd vvadd_fw \ - vvmul_d \ - -rv64uv_sc_vec_tests = \ - beq bge bgeu blt bltu bne \ - -rv64uv_p_tests = $(addprefix rv64uv-p-, $(rv64uv_sc_tests)) -rv64uv_pt_tests = $(addprefix rv64uv-pt-, $(rv64uv_sc_tests)) -rv64uv_v_tests = $(addprefix rv64uv-v-, $(rv64uv_sc_tests)) -rv64uv_p_vec_tests = $(addprefix rv64uv-p-vec-, $(rv64uv_sc_vec_tests)) -rv64uv_pt_vec_tests = $(addprefix rv64uv-pt-vec-, $(rv64uv_sc_vec_tests)) -rv64uv_v_vec_tests = $(addprefix rv64uv-v-vec-, $(rv64uv_sc_vec_tests)) - -spike_tests += $(rv64uv_p_tests) $(rv64uv_pt_tests) $(rv64uv_v_tests) diff --git a/isa/rv64uv/amoadd_d.S b/isa/rv64uv/amoadd_d.S deleted file mode 100644 index a90fb10..0000000 --- a/isa/rv64uv/amoadd_d.S +++ /dev/null @@ -1,58 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoadd_d.S -#----------------------------------------------------------------------------- -# -# Test amoadd.d instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a4,2048 - vsetvl a4,a4 - - la a5,amodest - vmsv vx2,a5 - li a5,1 - vmsv vx3,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsd vx1,a6 - fence - - li a1,0 -loop: - ld a0,0(a6) - addi TESTNUM,a1,2 - bne a0,a1,fail - addi a6,a6,8 - addi a1,a1,1 - bne a1,a4,loop - j pass - -vtcode: - amoadd.d x1,x3,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -amodest: - .dword 0 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/amoadd_w.S b/isa/rv64uv/amoadd_w.S deleted file mode 100644 index c0005b0..0000000 --- a/isa/rv64uv/amoadd_w.S +++ /dev/null @@ -1,58 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoadd_w.S -#----------------------------------------------------------------------------- -# -# Test amoadd.w instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a4,2048 - vsetvl a4,a4 - - la a5,amodest - vmsv vx2,a5 - li a5,1 - vmsv vx3,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsw vx1,a6 - fence - - li a1,0 -loop: - lw a0,0(a6) - addi TESTNUM,a1,2 - bne a0,a1,fail - addi a6,a6,4 - addi a1,a1,1 - bne a1,a4,loop - j pass - -vtcode: - amoadd.w x1,x3,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -amodest: - .word 0 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/amoand_d.S b/isa/rv64uv/amoand_d.S deleted file mode 100644 index e9e835d..0000000 --- a/isa/rv64uv/amoand_d.S +++ /dev/null @@ -1,58 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoand_d.S -#----------------------------------------------------------------------------- -# -# Test amoand.d instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a4,2048 - vsetvl a4,a4 - - la a5,amodest - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsd vx1,a6 - fence - - li a1,0 - li a2,0 -loop: - ld a0,0(a6) - addi TESTNUM,a1,2 - bne a0,a2,fail - addi a6,a6,8 - addi a1,a1,1 - bne a1,a4,loop - j pass - -vtcode: - li x3,-1 - amoand.d x1,x3,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -amodest: - .dword 0 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/amoand_w.S b/isa/rv64uv/amoand_w.S deleted file mode 100644 index 2dcb343..0000000 --- a/isa/rv64uv/amoand_w.S +++ /dev/null @@ -1,58 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoand_w.S -#----------------------------------------------------------------------------- -# -# Test amoand.w instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a4,2048 - vsetvl a4,a4 - - la a5,amodest - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsw vx1,a6 - fence - - li a1,0 - li a2,0 -loop: - lw a0,0(a6) - addi TESTNUM,a1,2 - bne a0,a2,fail - addi a6,a6,4 - addi a1,a1,1 - bne a1,a4,loop - j pass - -vtcode: - li x3,-1 - amoand.w x1,x3,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -amodest: - .word 0 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/amomax_d.S b/isa/rv64uv/amomax_d.S deleted file mode 100644 index 321a43f..0000000 --- a/isa/rv64uv/amomax_d.S +++ /dev/null @@ -1,61 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomax_d.S -#----------------------------------------------------------------------------- -# -# Test amomax.d instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a4,2048 - vsetvl a4,a4 - - la a5,amodest - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsd vx1,a6 - fence - - li a1,0 - li a2,0 -loop: - ld a0,0(a6) - addi TESTNUM,a1,2 - bne a0,a2,fail - addi a6,a6,8 - addi a1,a1,1 - bne a1,a4,loop - j pass - -vtcode: - utidx x3 - addi x3,x3,1 - li x1,-1 - mul x3,x3,x1 - amomax.d x1,x3,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -amodest: - .dword 0 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/amomax_w.S b/isa/rv64uv/amomax_w.S deleted file mode 100644 index e49d4ed..0000000 --- a/isa/rv64uv/amomax_w.S +++ /dev/null @@ -1,61 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomax_w.S -#----------------------------------------------------------------------------- -# -# Test amomax.w instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a4,2048 - vsetvl a4,a4 - - la a5,amodest - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsw vx1,a6 - fence - - li a1,0 - li a2,0 -loop: - lw a0,0(a6) - addi TESTNUM,a1,2 - bne a0,a2,fail - addi a6,a6,4 - addi a1,a1,1 - bne a1,a4,loop - j pass - -vtcode: - utidx x3 - addi x3,x3,1 - li x1,-1 - mul x3,x3,x1 - amomax.w x1,x3,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -amodest: - .word 0 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/amomaxu_d.S b/isa/rv64uv/amomaxu_d.S deleted file mode 100644 index 77162e5..0000000 --- a/isa/rv64uv/amomaxu_d.S +++ /dev/null @@ -1,61 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomaxu_d.S -#----------------------------------------------------------------------------- -# -# Test amomaxu.d instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a4,2048 - vsetvl a4,a4 - - la a5,amodest - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsd vx1,a6 - fence - - li a1,0 - li a2,-1 -loop: - ld a0,0(a6) - addi TESTNUM,a1,2 - bne a0,a2,fail - addi a6,a6,8 - addi a1,a1,1 - bne a1,a4,loop - j pass - -vtcode: - utidx x3 - addi x3,x3,1 - li x1,-1 - mul x3,x3,x1 - amomaxu.d x1,x3,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -amodest: - .dword -1 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/amomaxu_w.S b/isa/rv64uv/amomaxu_w.S deleted file mode 100644 index 83250eb..0000000 --- a/isa/rv64uv/amomaxu_w.S +++ /dev/null @@ -1,61 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomaxu_w.S -#----------------------------------------------------------------------------- -# -# Test amomaxu.w instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a4,2048 - vsetvl a4,a4 - - la a5,amodest - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsw vx1,a6 - fence - - li a1,0 - li a2,-1 -loop: - lw a0,0(a6) - addi TESTNUM,a1,2 - bne a0,a2,fail - addi a6,a6,4 - addi a1,a1,1 - bne a1,a4,loop - j pass - -vtcode: - utidx x3 - addi x3,x3,1 - li x1,-1 - mul x3,x3,x1 - amomaxu.w x1,x3,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -amodest: - .word -1 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/amomin_d.S b/isa/rv64uv/amomin_d.S deleted file mode 100644 index 2921884..0000000 --- a/isa/rv64uv/amomin_d.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomin_d.S -#----------------------------------------------------------------------------- -# -# Test amomin.d instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a4,2048 - vsetvl a4,a4 - - la a5,amodest - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsd vx1,a6 - fence - - li a1,0 - li a2,-1 -loop: - ld a0,0(a5) - addi TESTNUM,a1,2 - bne a0,a2,fail - addi a5,a5,8 - addi a1,a1,1 - addi a2,a2,-1 - bne a1,a4,loop - j pass - -vtcode: - utidx x3 - slli x3, x3, 3 - add x2, x2, x3 - utidx x3 - addi x3,x3,1 - li x1,-1 - mul x3,x3,x1 - amomin.d x1,x3,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -amodest: - .skip 16384 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/amomin_w.S b/isa/rv64uv/amomin_w.S deleted file mode 100644 index 18d71b7..0000000 --- a/isa/rv64uv/amomin_w.S +++ /dev/null @@ -1,62 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomin_w.S -#----------------------------------------------------------------------------- -# -# Test amomin.w instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a4,2048 - vsetvl a4,a4 - - la a5,amodest - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsw vx1,a6 - fence - - li a1,0 - li a2,0 -loop: - lw a0,0(a6) - addi TESTNUM,a1,2 - bne a0,a2,fail - addi a6,a6,4 - addi a1,a1,1 - addi a2,a2,-1 - bne a1,a4,loop - j pass - -vtcode: - utidx x3 - addi x3,x3,1 - li x1,-1 - mul x3,x3,x1 - amomin.w x1,x3,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -amodest: - .word 0 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/amominu_d.S b/isa/rv64uv/amominu_d.S deleted file mode 100644 index ed61a99..0000000 --- a/isa/rv64uv/amominu_d.S +++ /dev/null @@ -1,61 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amominu_d.S -#----------------------------------------------------------------------------- -# -# Test amominu.d instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a4,2048 - vsetvl a4,a4 - - la a5,amodest - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsd vx1,a6 - fence - - li a1,0 - li a2,0 -loop: - ld a0,0(a6) - addi TESTNUM,a1,2 - bne a0,a2,fail - addi a6,a6,8 - addi a1,a1,1 - bne a1,a4,loop - j pass - -vtcode: - utidx x3 - addi x3,x3,1 - li x1,-1 - mul x3,x3,x1 - amominu.d x1,x3,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -amodest: - .dword 0 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/amominu_w.S b/isa/rv64uv/amominu_w.S deleted file mode 100644 index 4e9544b..0000000 --- a/isa/rv64uv/amominu_w.S +++ /dev/null @@ -1,61 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amominu_w.S -#----------------------------------------------------------------------------- -# -# Test amominu.w instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a4,2048 - vsetvl a4,a4 - - la a5,amodest - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsw vx1,a6 - fence - - li a1,0 - li a2,0 -loop: - lw a0,0(a6) - addi TESTNUM,a1,2 - bne a0,a2,fail - addi a6,a6,4 - addi a1,a1,1 - bne a1,a4,loop - j pass - -vtcode: - utidx x3 - addi x3,x3,1 - li x1,-1 - mul x3,x3,x1 - amominu.w x1,x3,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -amodest: - .word 0 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/amoor_d.S b/isa/rv64uv/amoor_d.S deleted file mode 100644 index a7bdf52..0000000 --- a/isa/rv64uv/amoor_d.S +++ /dev/null @@ -1,58 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoor_d.S -#----------------------------------------------------------------------------- -# -# Test amoor.d instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a4,2048 - vsetvl a4,a4 - - la a5,amodest - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsd vx1,a6 - fence - - li a1,0 - li a2,-1 -loop: - ld a0,0(a6) - addi TESTNUM,a1,2 - bne a0,a2,fail - addi a6,a6,8 - addi a1,a1,1 - bne a1,a4,loop - j pass - -vtcode: - li x3,7 - amoor.d x1,x3,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -amodest: - .dword -1 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/amoor_w.S b/isa/rv64uv/amoor_w.S deleted file mode 100644 index db1f275..0000000 --- a/isa/rv64uv/amoor_w.S +++ /dev/null @@ -1,58 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoor_w.S -#----------------------------------------------------------------------------- -# -# Test amoor.w instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a4,2048 - vsetvl a4,a4 - - la a5,amodest - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsw vx1,a6 - fence - - li a1,0 - li a2,-1 -loop: - lw a0,0(a6) - addi TESTNUM,a1,2 - bne a0,a2,fail - addi a6,a6,4 - addi a1,a1,1 - bne a1,a4,loop - j pass - -vtcode: - li x3,7 - amoor.w x1,x3,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -amodest: - .word -1 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/amoswap_d.S b/isa/rv64uv/amoswap_d.S deleted file mode 100644 index 8b2aa87..0000000 --- a/isa/rv64uv/amoswap_d.S +++ /dev/null @@ -1,58 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoswap_d.S -#----------------------------------------------------------------------------- -# -# Test amoswap.d instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a4,2048 - vsetvl a4,a4 - - la a5,amodest - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsd vx1,a6 - fence - - li a1,0 -loop: - ld a0,0(a6) - addi TESTNUM,a1,2 - bne a0,a1,fail - addi a6,a6,8 - addi a1,a1,1 - bne a1,a4,loop - j pass - -vtcode: - utidx x3 - addi x3,x3,1 - amoswap.d x1,x3,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -amodest: - .dword 0 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/amoswap_w.S b/isa/rv64uv/amoswap_w.S deleted file mode 100644 index dd1a837..0000000 --- a/isa/rv64uv/amoswap_w.S +++ /dev/null @@ -1,58 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoswap_w.S -#----------------------------------------------------------------------------- -# -# Test amoswap.w instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a4,2048 - vsetvl a4,a4 - - la a5,amodest - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsw vx1,a6 - fence - - li a1,0 -loop: - lw a0,0(a6) - addi TESTNUM,a1,2 - bne a0,a1,fail - addi a6,a6,4 - addi a1,a1,1 - bne a1,a4,loop - j pass - -vtcode: - utidx x3 - addi x3,x3,1 - amoswap.w x1,x3,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -amodest: - .word 0 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/amoxor_d.S b/isa/rv64uv/amoxor_d.S deleted file mode 100644 index 78cb310..0000000 --- a/isa/rv64uv/amoxor_d.S +++ /dev/null @@ -1,60 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoxor_d.S -#----------------------------------------------------------------------------- -# -# Test amoxor.d instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a4,2048 - vsetvl a4,a4 - - la a5,amodest - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsd vx1,a6 - fence - - li a1,0 - li a2,-1 - li t0,0xaaaaaaaaaaaaaaaa -loop: - ld a0,0(a6) - addi TESTNUM,a1,2 - bne a0,a2,fail - addi a6,a6,8 - addi a1,a1,1 - xor a2,a2,t0 - bne a1,a4,loop - j pass - -vtcode: - li x3,0xaaaaaaaaaaaaaaaa - amoxor.d x1,x3,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -amodest: - .dword -1 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/amoxor_w.S b/isa/rv64uv/amoxor_w.S deleted file mode 100644 index 6eee508..0000000 --- a/isa/rv64uv/amoxor_w.S +++ /dev/null @@ -1,60 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoxor_w.S -#----------------------------------------------------------------------------- -# -# Test amoxor.w instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a4,2048 - vsetvl a4,a4 - - la a5,amodest - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsw vx1,a6 - fence - - li a1,0 - li a2,-1 -loop: - lw a0,0(a6) - addi TESTNUM,a1,2 - bne a0,a2,fail - addi a6,a6,4 - addi a1,a1,1 - li t0,0xcafe - xor a2,a2,t0 - bne a1,a4,loop - j pass - -vtcode: - li x3,0xcafe - amoxor.w x1,x3,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -amodest: - .word -1 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/beq.S b/isa/rv64uv/beq.S deleted file mode 100644 index 8c7bce4..0000000 --- a/isa/rv64uv/beq.S +++ /dev/null @@ -1,96 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# beq.S -#----------------------------------------------------------------------------- -# -# Test beq instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Branch tests - #------------------------------------------------------------- - - # Each test checks both forward and backward branches - - TEST_BR2_OP_TAKEN( 2, beq, 0, 0 ); - TEST_BR2_OP_TAKEN( 3, beq, 1, 1 ); - TEST_BR2_OP_TAKEN( 4, beq, -1, -1 ); - - TEST_BR2_OP_NOTTAKEN( 5, beq, 0, 1 ); - TEST_BR2_OP_NOTTAKEN( 6, beq, 1, 0 ); - TEST_BR2_OP_NOTTAKEN( 7, beq, -1, 1 ); - TEST_BR2_OP_NOTTAKEN( 8, beq, 1, -1 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_BR2_SRC12_BYPASS( 9, 0, 0, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 10, 0, 1, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 11, 0, 2, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 12, 1, 0, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 13, 1, 1, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 14, 2, 0, beq, 0, -1 ); - - TEST_BR2_SRC12_BYPASS( 15, 0, 0, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 16, 0, 1, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 17, 0, 2, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 18, 1, 0, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 19, 1, 1, beq, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 20, 2, 0, beq, 0, -1 ); - - #------------------------------------------------------------- - # Test when uts diverge - #------------------------------------------------------------- - - TEST_BR2_DIVERGED_ODD_EVEN( 24, beq, 1, 1, \ - addi x3, x3, 1; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 25, beq, 2, 2, \ - addi x3, x3, 1; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 26, beq, 3, 3, \ - addi x3, x3, 1; \ - ) - - TEST_BR2_DIVERGED_ODD_EVEN( 27, beq, 1, 16, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 28, beq, 2, 400, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 29, beq, 3, 163216, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - - TEST_BR2_DIVERGED_FULL12( 30, beq, 1, 1, \ - addi x3, x3, 1; \ - ) - - TEST_BR2_DIVERGED_FULL12( 31, beq, 1, 16, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - - TEST_BR2_DIVERGED_MEM_FULL12( 32, beq, 1); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64uv/bge.S b/isa/rv64uv/bge.S deleted file mode 100644 index 6763a1c..0000000 --- a/isa/rv64uv/bge.S +++ /dev/null @@ -1,99 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# bge.S -#----------------------------------------------------------------------------- -# -# Test bge instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Branch tests - #------------------------------------------------------------- - - # Each test checks both forward and backward branches - - TEST_BR2_OP_TAKEN( 2, bge, 0, 0 ); - TEST_BR2_OP_TAKEN( 3, bge, 1, 1 ); - TEST_BR2_OP_TAKEN( 4, bge, -1, -1 ); - TEST_BR2_OP_TAKEN( 5, bge, 1, 0 ); - TEST_BR2_OP_TAKEN( 6, bge, 1, -1 ); - TEST_BR2_OP_TAKEN( 7, bge, -1, -2 ); - - TEST_BR2_OP_NOTTAKEN( 8, bge, 0, 1 ); - TEST_BR2_OP_NOTTAKEN( 9, bge, -1, 1 ); - TEST_BR2_OP_NOTTAKEN( 10, bge, -2, -1 ); - TEST_BR2_OP_NOTTAKEN( 11, bge, -2, 1 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_BR2_SRC12_BYPASS( 12, 0, 0, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 13, 0, 1, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 14, 0, 2, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 15, 1, 0, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 16, 1, 1, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 17, 2, 0, bge, -1, 0 ); - - TEST_BR2_SRC12_BYPASS( 18, 0, 0, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 19, 0, 1, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 20, 0, 2, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 21, 1, 0, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 22, 1, 1, bge, -1, 0 ); - TEST_BR2_SRC12_BYPASS( 23, 2, 0, bge, -1, 0 ); - - #------------------------------------------------------------- - # Test when uts diverge - #------------------------------------------------------------- - - TEST_BR2_DIVERGED_ODD_EVEN( 24, bge, 1, 1, \ - addi x3, x3, 1; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 25, bge, 2, 2, \ - addi x3, x3, 1; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 26, bge, 3, 3, \ - addi x3, x3, 1; \ - ) - - TEST_BR2_DIVERGED_ODD_EVEN( 27, bge, 1, 16, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 28, bge, 2, 400, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 29, bge, 3, 163216, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - - TEST_BR2_DIVERGED_FULL12( 30, bge, 1, 1, \ - addi x3, x3, 1; \ - ) - - TEST_BR2_DIVERGED_FULL12( 31, bge, 1, 16, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - - TEST_BR2_DIVERGED_MEM_FULL12( 32, bge, 1); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64uv/bgeu.S b/isa/rv64uv/bgeu.S deleted file mode 100644 index 527e446..0000000 --- a/isa/rv64uv/bgeu.S +++ /dev/null @@ -1,99 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# bgeu.S -#----------------------------------------------------------------------------- -# -# Test bgeu instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Branch tests - #------------------------------------------------------------- - - # Each test checks both forward and backward branches - - TEST_BR2_OP_TAKEN( 2, bgeu, 0x00000000, 0x00000000 ); - TEST_BR2_OP_TAKEN( 3, bgeu, 0x00000001, 0x00000001 ); - TEST_BR2_OP_TAKEN( 4, bgeu, 0xffffffff, 0xffffffff ); - TEST_BR2_OP_TAKEN( 5, bgeu, 0x00000001, 0x00000000 ); - TEST_BR2_OP_TAKEN( 6, bgeu, 0xffffffff, 0xfffffffe ); - TEST_BR2_OP_TAKEN( 7, bgeu, 0xffffffff, 0x00000000 ); - - TEST_BR2_OP_NOTTAKEN( 8, bgeu, 0x00000000, 0x00000001 ); - TEST_BR2_OP_NOTTAKEN( 9, bgeu, 0xfffffffe, 0xffffffff ); - TEST_BR2_OP_NOTTAKEN( 10, bgeu, 0x00000000, 0xffffffff ); - TEST_BR2_OP_NOTTAKEN( 11, bgeu, 0x7fffffff, 0x80000000 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_BR2_SRC12_BYPASS( 12, 0, 0, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 13, 0, 1, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 14, 0, 2, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 15, 1, 0, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 16, 1, 1, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 17, 2, 0, bgeu, 0xefffffff, 0xf0000000 ); - - TEST_BR2_SRC12_BYPASS( 18, 0, 0, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 19, 0, 1, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 20, 0, 2, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 21, 1, 0, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 22, 1, 1, bgeu, 0xefffffff, 0xf0000000 ); - TEST_BR2_SRC12_BYPASS( 23, 2, 0, bgeu, 0xefffffff, 0xf0000000 ); - - #------------------------------------------------------------- - # Test when uts diverge - #------------------------------------------------------------- - - TEST_BR2_DIVERGED_ODD_EVEN( 24, bgeu, 1, 1, \ - addi x3, x3, 1; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 25, bgeu, 2, 2, \ - addi x3, x3, 1; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 26, bgeu, 3, 3, \ - addi x3, x3, 1; \ - ) - - TEST_BR2_DIVERGED_ODD_EVEN( 27, bgeu, 1, 16, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 28, bgeu, 2, 400, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 29, bgeu, 3, 163216, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - - TEST_BR2_DIVERGED_FULL12( 30, bgeu, 1, 1, \ - addi x3, x3, 1; \ - ) - - TEST_BR2_DIVERGED_FULL12( 31, bgeu, 1, 16, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - - TEST_BR2_DIVERGED_MEM_FULL12( 32, bgeu, 1); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64uv/blt.S b/isa/rv64uv/blt.S deleted file mode 100644 index 575b85c..0000000 --- a/isa/rv64uv/blt.S +++ /dev/null @@ -1,96 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# blt.S -#----------------------------------------------------------------------------- -# -# Test blt instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Branch tests - #------------------------------------------------------------- - - # Each test checks both forward and backward branches - - TEST_BR2_OP_TAKEN( 2, blt, 0, 1 ); - TEST_BR2_OP_TAKEN( 3, blt, -1, 1 ); - TEST_BR2_OP_TAKEN( 4, blt, -2, -1 ); - - TEST_BR2_OP_NOTTAKEN( 5, blt, 1, 0 ); - TEST_BR2_OP_NOTTAKEN( 6, blt, 1, -1 ); - TEST_BR2_OP_NOTTAKEN( 7, blt, -1, -2 ); - TEST_BR2_OP_NOTTAKEN( 8, blt, 1, -2 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_BR2_SRC12_BYPASS( 9, 0, 0, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 10, 0, 1, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 11, 0, 2, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 12, 1, 0, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 13, 1, 1, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 14, 2, 0, blt, 0, -1 ); - - TEST_BR2_SRC12_BYPASS( 15, 0, 0, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 16, 0, 1, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 17, 0, 2, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 18, 1, 0, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 19, 1, 1, blt, 0, -1 ); - TEST_BR2_SRC12_BYPASS( 20, 2, 0, blt, 0, -1 ); - - #------------------------------------------------------------- - # Test when uts diverge - #------------------------------------------------------------- - - TEST_BR2_DIVERGED_ODD_EVEN( 24, blt, 1, 1, \ - addi x3, x3, 1; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 25, blt, 2, 2, \ - addi x3, x3, 1; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 26, blt, 3, 3, \ - addi x3, x3, 1; \ - ) - - TEST_BR2_DIVERGED_ODD_EVEN( 27, blt, 1, 16, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 28, blt, 2, 400, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 29, blt, 3, 163216, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - - TEST_BR2_DIVERGED_FULL21( 30, blt, 0, 1, \ - addi x3, x3, 1; \ - ) - - TEST_BR2_DIVERGED_FULL21( 31, blt, 0, 16, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - - TEST_BR2_DIVERGED_MEM_FULL21( 32, blt, 0); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64uv/bltu.S b/isa/rv64uv/bltu.S deleted file mode 100644 index d499531..0000000 --- a/isa/rv64uv/bltu.S +++ /dev/null @@ -1,96 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# bltu.S -#----------------------------------------------------------------------------- -# -# Test bltu instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Branch tests - #------------------------------------------------------------- - - # Each test checks both forward and backward branches - - TEST_BR2_OP_TAKEN( 2, bltu, 0x00000000, 0x00000001 ); - TEST_BR2_OP_TAKEN( 3, bltu, 0xfffffffe, 0xffffffff ); - TEST_BR2_OP_TAKEN( 4, bltu, 0x00000000, 0xffffffff ); - - TEST_BR2_OP_NOTTAKEN( 5, bltu, 0x00000001, 0x00000000 ); - TEST_BR2_OP_NOTTAKEN( 6, bltu, 0xffffffff, 0xfffffffe ); - TEST_BR2_OP_NOTTAKEN( 7, bltu, 0xffffffff, 0x00000000 ); - TEST_BR2_OP_NOTTAKEN( 8, bltu, 0x80000000, 0x7fffffff ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_BR2_SRC12_BYPASS( 9, 0, 0, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 10, 0, 1, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 11, 0, 2, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 12, 1, 0, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 13, 1, 1, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 14, 2, 0, bltu, 0xf0000000, 0xefffffff ); - - TEST_BR2_SRC12_BYPASS( 15, 0, 0, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 16, 0, 1, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 17, 0, 2, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 18, 1, 0, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 19, 1, 1, bltu, 0xf0000000, 0xefffffff ); - TEST_BR2_SRC12_BYPASS( 20, 2, 0, bltu, 0xf0000000, 0xefffffff ); - - #------------------------------------------------------------- - # Test when uts diverge - #------------------------------------------------------------- - - TEST_BR2_DIVERGED_ODD_EVEN( 24, bltu, 1, 1, \ - addi x3, x3, 1; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 25, bltu, 2, 2, \ - addi x3, x3, 1; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 26, bltu, 3, 3, \ - addi x3, x3, 1; \ - ) - - TEST_BR2_DIVERGED_ODD_EVEN( 27, bltu, 1, 16, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 28, bltu, 2, 400, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 29, bltu, 3, 163216, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - - TEST_BR2_DIVERGED_FULL21( 30, bltu, 0, 1, \ - addi x3, x3, 1; \ - ) - - TEST_BR2_DIVERGED_FULL21( 31, bltu, 0, 16, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - - TEST_BR2_DIVERGED_MEM_FULL21( 32, bltu, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64uv/bne.S b/isa/rv64uv/bne.S deleted file mode 100644 index 6b01d9b..0000000 --- a/isa/rv64uv/bne.S +++ /dev/null @@ -1,96 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# bne.S -#----------------------------------------------------------------------------- -# -# Test bne instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Branch tests - #------------------------------------------------------------- - - # Each test checks both forward and backward branches - - TEST_BR2_OP_TAKEN( 2, bne, 0, 1 ); - TEST_BR2_OP_TAKEN( 3, bne, 1, 0 ); - TEST_BR2_OP_TAKEN( 4, bne, -1, 1 ); - TEST_BR2_OP_TAKEN( 5, bne, 1, -1 ); - - TEST_BR2_OP_NOTTAKEN( 6, bne, 0, 0 ); - TEST_BR2_OP_NOTTAKEN( 7, bne, 1, 1 ); - TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_BR2_SRC12_BYPASS( 9, 0, 0, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 10, 0, 1, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 11, 0, 2, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 12, 1, 0, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 13, 1, 1, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 14, 2, 0, bne, 0, 0 ); - - TEST_BR2_SRC12_BYPASS( 15, 0, 0, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 16, 0, 1, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 17, 0, 2, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 18, 1, 0, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 19, 1, 1, bne, 0, 0 ); - TEST_BR2_SRC12_BYPASS( 20, 2, 0, bne, 0, 0 ); - - #------------------------------------------------------------- - # Test when uts diverge - #------------------------------------------------------------- - - TEST_BR2_DIVERGED_ODD_EVEN( 24, bne, 1, 1, \ - addi x3, x3, 1; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 25, bne, 2, 2, \ - addi x3, x3, 1; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 26, bne, 3, 3, \ - addi x3, x3, 1; \ - ) - - TEST_BR2_DIVERGED_ODD_EVEN( 27, bne, 1, 16, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 28, bne, 2, 400, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - TEST_BR2_DIVERGED_ODD_EVEN( 29, bne, 3, 163216, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - - TEST_BR2_DIVERGED_FULL12( 30, bne, 0, 1, \ - addi x3, x3, 1; \ - ) - - TEST_BR2_DIVERGED_FULL12( 31, bne, 0, 16, \ - addi x3, x3, 4; \ - mul x3, x3, x3; \ - ) - - TEST_BR2_DIVERGED_MEM_FULL12( 32, bne, 0); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64uv/data_d.h b/isa/rv64uv/data_d.h deleted file mode 100644 index 98a3eb2..0000000 --- a/isa/rv64uv/data_d.h +++ /dev/null @@ -1,4098 +0,0 @@ -# See LICENSE for license details. - -.dword 0xd1dd560bfe643843 -.dword 0xc8ad10b2feb2c113 -.dword 0xa6ce19b8a92a9e4a -.dword 0x6fb83883fbe60922 -.dword 0xcd6d2e7ead7330da -.dword 0xb755598a5cfbe06d -.dword 0x1fed84bdc9a118eb -.dword 0x24b3f3d23d84f322 -.dword 0x1d3a988f53778458 -.dword 0x9f730b0a1f140995 -.dword 0x374b360639302b65 -.dword 0xc88b9497f9b5efd5 -.dword 0x0f172d3a9a63bd97 -.dword 0xc972275f26cd737e -.dword 0x0c78f61b7c470f8a -.dword 0x4def0e021a99b81b -.dword 0x4390f30c5a5c55b8 -.dword 0xeaf430769db34de0 -.dword 0x8e8fc37e74e9f4db -.dword 0xcc629a32e15f65e2 -.dword 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-RVTEST_CODE_BEGIN - - vsetcfg 32,32 - li a3,4 - vsetvl a3,a3 - - la a3,src - vld vx2,a3 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a4,dest - vfsd vf0,a4 - fence - la a5,result - ld a1,0(a4) - ld a2,0(a5) - li TESTNUM,2 - bne a1,a2,fail - ld a1,8(a4) - ld a2,8(a5) - li TESTNUM,3 - bne a1,a2,fail - ld a1,16(a4) - ld a2,16(a5) - li TESTNUM,4 - bne a1,a2,fail - ld a1,24(a4) - ld a2,24(a5) - li TESTNUM,5 - bne a1,a2,fail - j pass - -vtcode: - fcvt.d.l f0,x2 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src: - .dword 1 - .dword 2 - .dword 3 - .dword 4 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe -result: - .double 1.0 - .double 2.0 - .double 3.0 - .double 4.0 - -RVTEST_DATA_END diff --git a/isa/rv64uv/fence.S b/isa/rv64uv/fence.S deleted file mode 100644 index 1a50807..0000000 --- a/isa/rv64uv/fence.S +++ /dev/null @@ -1,61 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# fence.S -#----------------------------------------------------------------------------- -# -# Test fence instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - # make sure these don't choke at the beginning - fence - fence rw,io - fence io,rw - fence r,io - fence w,io - fence rw,i - fence rw,o - - li a0,1 - bne a0,x0,skip1 - fence -skip1: - - bne a0,x0,skip3 - fence -skip3: - - j pass - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .dword 1 - .dword 2 - .dword 3 - .dword 4 -src2: - .dword 4 - .dword 3 - .dword 2 - .dword 1 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - -RVTEST_DATA_END diff --git a/isa/rv64uv/fld.S b/isa/rv64uv/fld.S deleted file mode 100644 index 8c87387..0000000 --- a/isa/rv64uv/fld.S +++ /dev/null @@ -1,62 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# fld.S -#----------------------------------------------------------------------------- -# -# Test fld instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,1 - li a4,512 - vsetvl a4,a4 - - la a5,src - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vfsd vf0,a6 - fence - - li a2,0 -loop: - ld a0,0(a6) - addi TESTNUM,a2,2 - ld a1,0(a5) - bne a0,a1,fail - addi a6,a6,8 - addi a5,a5,8 - addi a2,a2,1 - bne a2,a4,loop - j pass - -vtcode: - utidx x3 - slli x3,x3,3 - add x2,x2,x3 - fld f0,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src: -#include "data_fd.h" - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/flw.S b/isa/rv64uv/flw.S deleted file mode 100644 index 6d6353c..0000000 --- a/isa/rv64uv/flw.S +++ /dev/null @@ -1,62 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# flw.S -#----------------------------------------------------------------------------- -# -# Test flw instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,1 - li a4,2048 - vsetvl a4,a4 - - la a5,src - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vfsw vf0,a6 - fence - - li a2,0 -loop: - lw a0,0(a6) - addi TESTNUM,a2,2 - lw a1,0(a5) - bne a0,a1,fail - addi a6,a6,4 - addi a5,a5,4 - addi a2,a2,1 - bne a2,a4,loop - j pass - -vtcode: - utidx x3 - slli x3,x3,2 - add x2,x2,x3 - flw f0,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src: -#include "data_fw.h" - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/fma.S b/isa/rv64uv/fma.S deleted file mode 100644 index 454d736..0000000 --- a/isa/rv64uv/fma.S +++ /dev/null @@ -1,81 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# fma.S -#----------------------------------------------------------------------------- -# -# Test fma instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 3,2 - li a3,2048 - vsetvl a3,a3 - - la a4,src - fld f0,0(a4) - fld f1,8(a4) - fmv.x.d s0,f0 - fmv.x.d s1,f1 - vmsv vx1,s0 - vmsv vx2,s1 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - - li a7,0 - li a6,400 -wait: - addi a7,a7,1 - bne a7,a6,wait - - fadd.d f0,f0,f1 - fmv.x.d s2,f0 - - la a5,dest - vfsd vf0,a5 - fence - - la s3,result - ld s4,0(s3) - li TESTNUM,2 - bne s2,s4,fail - - li a2,0 -loop: - ld a0,0(a5) - addi TESTNUM,a2,3 - bne a0,s4,fail - addi a5,a5,8 - addi a2,a2,1 - bne a2,a3,loop - j pass - -vtcode: - fmv.d.x f0,x1 - fmv.d.x f1,x2 - fadd.d f0,f0,f1 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src: - .double 1.0 - .double 2.0 -result: - .double 3.0 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/fma_many.S b/isa/rv64uv/fma_many.S deleted file mode 100644 index b72b670..0000000 --- a/isa/rv64uv/fma_many.S +++ /dev/null @@ -1,182 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# fma.S -#----------------------------------------------------------------------------- -# -# Test fma instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 3,16 - li a3,2048 - vsetvl a3,a3 - - la a4,src - fld f0,0(a4) - fld f1,8(a4) - fmv.x.d s0,f0 - fmv.x.d s1,f1 - vmsv vx1,s0 - vmsv vx2,s1 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - - li a7,0 - li a6,400 -wait: - addi a7,a7,1 - bne a7,a6,wait - - fadd.d f0,f0,f1 - fmv.x.d s2,f0 - - la a5,dest - vfsd vf0,a5 - fence - - la s3,result - ld s4,0(s3) - li TESTNUM,2 - bne s2,s4,fail - -# verify 1st fadd - li a2,0 -loop1: - ld a0,0(a5) - addi TESTNUM,a2,3 - bne a0,s4,fail - addi a5,a5,8 - addi a2,a2,1 - bne a2,a3,loop1 - -# verify 2nd fmadd - la a5,dest - vfsd vf2,a5 - fence - ld s4,8(s3) - - li a2,0 -loop2: - ld a0,0(a5) - addi TESTNUM,a2,3 - bne a0,s4,fail - addi a5,a5,8 - addi a2,a2,1 - bne a2,a3,loop2 - -# verify 3rd fmul - la a5,dest - vfsd vf5,a5 - fence - ld s4,16(s3) - - li a2,0 -loop3: - ld a0,0(a5) - addi TESTNUM,a2,3 - bne a0,s4,fail - addi a5,a5,8 - addi a2,a2,1 - bne a2,a3,loop3 - -# verify 4th fmul - la a5,dest - vfsd vf8,a5 - fence - ld s4,24(s3) - - li a2,0 -loop4: - ld a0,0(a5) - addi TESTNUM,a2,3 - bne a0,s4,fail - addi a5,a5,8 - addi a2,a2,1 - bne a2,a3,loop4 - -# verify 5th fmadd - la a5,dest - vfsd vf9,a5 - fence - ld s4,32(s3) - - li a2,0 -loop5: - ld a0,0(a5) - addi TESTNUM,a2,3 - bne a0,s4,fail - addi a5,a5,8 - addi a2,a2,1 - bne a2,a3,loop5 - -# verify 6th fnmadd - la a5,dest - vfsd vf11,a5 - fence - ld s4,40(s3) - - li a2,0 -loop6: - ld a0,0(a5) - addi TESTNUM,a2,3 - bne a0,s4,fail - addi a5,a5,8 - addi a2,a2,1 - bne a2,a3,loop6 - - j pass - -vtcode: - fmv.d.x f0,x1 - fmv.d.x f1,x2 - fmv.d.x f2,x1 - fmv.d.x f3,x2 - fmv.d.x f4,x1 - fmv.d.x f5,x2 - fmv.d.x f6,x1 - fmv.d.x f7,x2 - fmv.d.x f8,x1 - fmv.d.x f9,x2 - fmv.d.x f10,x1 - fmv.d.x f11,x2 - fmv.d.x f12,x1 - fmv.d.x f13,x2 - fmv.d.x f14,x1 - fmv.d.x f15,x2 - fadd.d f0,f0,f1 - fmadd.d f2,f2,f3,f4 - fmul.d f5,f5,f6 - fmul.d f8,f5,f7 - fmadd.d f9,f9,f10,f9 - fnmadd.d f11,f12,f13,f14 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src: - .double 1.0 - .double 2.0 -result: - .double 3.0 - .double 3.0 - .double 2.0 - .double 4.0 - .double 4.0 - .double -3.0 -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/fmovn.S b/isa/rv64uv/fmovn.S deleted file mode 100644 index 4442370..0000000 --- a/isa/rv64uv/fmovn.S +++ /dev/null @@ -1,63 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# fmovn.S -#----------------------------------------------------------------------------- -# -# Test fmovn instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,2 - li a6,2048 - vsetvl a6,a6 - - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a7,dest - vfsd vf0,a7 - fence - - li a1,0 - li a2,-1 -loop: - ld a0,0(a7) - slti a4,a1,10 - slli a4,a4,63 - srai a4,a4,63 - and a5,a2,a4 - addi TESTNUM,a1,2 - bne a0,a5,fail - addi a7,a7,8 - addi a1,a1,1 - bne a1,a6,loop - j pass - -vtcode: - utidx x1 - slti x2,x1,10 - li x1,-1 - li x3,0 - fmv.d.x f0,x3 - fmv.d.x f1,x1 - fmovn f0,x2,f1 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/fmovz.S b/isa/rv64uv/fmovz.S deleted file mode 100644 index 76583f5..0000000 --- a/isa/rv64uv/fmovz.S +++ /dev/null @@ -1,64 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# fmovz.S -#----------------------------------------------------------------------------- -# -# Test fmovz instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,2 - li a6,2048 - vsetvl a6,a6 - - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a7,dest - vfsd vf0,a7 - fence - - li a1,0 - li a2,-1 -loop: - ld a0,0(a7) - slti a4,a1,10 - slli a4,a4,63 - srai a4,a4,63 - xori a4,a4,-1 - and a5,a2,a4 - addi TESTNUM,a1,2 - bne a0,a5,fail - addi a7,a7,8 - addi a1,a1,1 - bne a1,a6,loop - j pass - -vtcode: - utidx x1 - slti x2,x1,10 - li x1,-1 - li x3,0 - fmv.d.x f0,x3 - fmv.d.x f1,x1 - fmovz f0,x2,f1 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/fsd.S b/isa/rv64uv/fsd.S deleted file mode 100644 index c1dd229..0000000 --- a/isa/rv64uv/fsd.S +++ /dev/null @@ -1,62 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# fsd.S -#----------------------------------------------------------------------------- -# -# Test fsd instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,1 - li a4,2048 - vsetvl a4,a4 - - la a5,src - vfld vf0,a5 - la a6,dest - vmsv vx2,a6 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - fence - - li a2,0 -loop: - ld a0,0(a6) - addi TESTNUM,a2,2 - ld a1,0(a5) - bne a0,a1,fail - addi a6,a6,8 - addi a5,a5,8 - addi a2,a2,1 - bne a2,a4,loop - j pass - -vtcode: - utidx x3 - slli x3,x3,3 - add x2,x2,x3 - fsd f0,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src: -#include "data_fd.h" - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/fsw.S b/isa/rv64uv/fsw.S deleted file mode 100644 index 9539a77..0000000 --- a/isa/rv64uv/fsw.S +++ /dev/null @@ -1,62 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# fsw.S -#----------------------------------------------------------------------------- -# -# Test fsw instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,1 - li a4,2048 - vsetvl a4,a4 - - la a5,src - vflw vf0,a5 - la a6,dest - vmsv vx2,a6 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - fence - - li a2,0 -loop: - lw a0,0(a6) - addi TESTNUM,a2,2 - lw a1,0(a5) - bne a0,a1,fail - addi a6,a6,4 - addi a5,a5,4 - addi a2,a2,1 - bne a2,a4,loop - j pass - -vtcode: - utidx x3 - slli x3,x3,2 - add x2,x2,x3 - fsw f0,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src: -#include "data_fw.h" - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/imul.S b/isa/rv64uv/imul.S deleted file mode 100644 index ebfb77d..0000000 --- a/isa/rv64uv/imul.S +++ /dev/null @@ -1,85 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# imul.S -#----------------------------------------------------------------------------- -# -# Test imul instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 3,0 - li a3,2048 - vsetvl a3,a3 - - li a4,20 - li s0,2 - vmsv vx1,a4 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - mul s1,a4,s0 - - la a5,dest - vsd vx1,a5 - fence - - li s2,40 - li TESTNUM,2 - bne s1,s2,fail - - li a1,0 - li a2,0 -loop: - ld a0,0(a5) - addi TESTNUM,a2,3 - bne a0,a1,fail - addi a5,a5,8 - addi a1,a1,20 - addi a2,a2,1 - bne a2,a3,loop - j pass - -vtcode: - utidx x2 - mul x1,x2,x1 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/keepcfg.S b/isa/rv64uv/keepcfg.S deleted file mode 100644 index 552b1c4..0000000 --- a/isa/rv64uv/keepcfg.S +++ /dev/null @@ -1,85 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# utidx.S -#----------------------------------------------------------------------------- -# -# Test utidx instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 2,0 - li s0,2048 - vsetvl s0,s0 - - lui a0,%hi(vtcode1) - vf %lo(vtcode1)(a0) - la a4,dest1 - vsd vx1,a4 - - vsetcfg 3,0 - li s1,2048 - vsetvl s1,s1 - - lui a0,%hi(vtcode2) - vf %lo(vtcode2)(a0) - la a4,dest2 - vsd vx1,a4 - - fence - - la a4,dest1 - li a1,1 -loop1: - ld a0,0(a4) - addi TESTNUM,a1,2 - bne a0,a1,fail - addi a4,a4,8 - addi a1,a1,1 - bne a1,s0,loop1 - - la a4,dest2 - li a1,1024 - li a2,1 -loop2: - ld a0,0(a4) - addi TESTNUM,a1,2 - bne a0,a1,fail - addi a4,a4,8 - addi a1,a1,1 - addi a2,a2,1 - bne a2,s1,loop2 - - j pass - -vtcode1: - utidx x1 - addi x1,x1,1 - stop - -vtcode2: - utidx x1 - addi x1,x1,1024 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -dest1: - .skip 16384 - -dest2: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/lb.S b/isa/rv64uv/lb.S deleted file mode 100644 index 2e79c13..0000000 --- a/isa/rv64uv/lb.S +++ /dev/null @@ -1,64 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# lb.S -#----------------------------------------------------------------------------- -# -# Test lb instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 16,0 - li a4,512 - vsetvl a4,a4 - - la a5,src - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsd vx1,a6 - fence - - li a2,0 -loop: - ld a0,0(a6) - ld a1,0(a5) - sll a3,a1,56 - sra a3,a3,56 - addi TESTNUM,a2,2 - bne a0,a3,fail - addi a6,a6,8 - addi a5,a5,8 - addi a2,a2,1 - bne a2,a4,loop - j pass - -vtcode: - utidx x3 - slli x3,x3,3 - add x2,x2,x3 - lb x1,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src: -#include "data_d.h" - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/lbu.S b/isa/rv64uv/lbu.S deleted file mode 100644 index fd04fdf..0000000 --- a/isa/rv64uv/lbu.S +++ /dev/null @@ -1,64 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# lbu.S -#----------------------------------------------------------------------------- -# -# Test lby instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 16,0 - li a4,512 - vsetvl a4,a4 - - la a5,src - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsd vx1,a6 - fence - - li a2,0 -loop: - ld a0,0(a6) - ld a1,0(a5) - sll a3,a1,56 - srl a3,a3,56 - addi TESTNUM,a2,2 - bne a0,a3,fail - addi a6,a6,8 - addi a5,a5,8 - addi a2,a2,1 - bne a2,a4,loop - j pass - -vtcode: - utidx x3 - slli x3,x3,3 - add x2,x2,x3 - lbu x1,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src: -#include "data_d.h" - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/ld.S b/isa/rv64uv/ld.S deleted file mode 100644 index e0f12fd..0000000 --- a/isa/rv64uv/ld.S +++ /dev/null @@ -1,62 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# ld.S -#----------------------------------------------------------------------------- -# -# Test ld instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 16,0 - li a4,512 - vsetvl a4,a4 - - la a5,src - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsd vx1,a6 - fence - - li a2,0 -loop: - ld a0,0(a6) - ld a1,0(a5) - addi TESTNUM,a2,2 - bne a0,a1,fail - addi a6,a6,8 - addi a5,a5,8 - addi a2,a2,1 - bne a2,a4,loop - j pass - -vtcode: - utidx x3 - slli x3,x3,3 - add x2,x2,x3 - ld x1,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src: -#include "data_d.h" - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/lh.S b/isa/rv64uv/lh.S deleted file mode 100644 index 62a1029..0000000 --- a/isa/rv64uv/lh.S +++ /dev/null @@ -1,64 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# lh.S -#----------------------------------------------------------------------------- -# -# Test lh instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 16,0 - li a4,512 - vsetvl a4,a4 - - la a5,src - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsd vx1,a6 - fence - - li a2,0 -loop: - ld a0,0(a6) - ld a1,0(a5) - sll a3,a1,48 - sra a3,a3,48 - addi TESTNUM,a2,2 - bne a0,a3,fail - addi a6,a6,8 - addi a5,a5,8 - addi a2,a2,1 - bne a2,a4,loop - j pass - -vtcode: - utidx x3 - slli x3,x3,3 - add x2,x2,x3 - lh x1,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src: -#include "data_d.h" - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/lhu.S b/isa/rv64uv/lhu.S deleted file mode 100644 index a2de42b..0000000 --- a/isa/rv64uv/lhu.S +++ /dev/null @@ -1,64 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# lhu.S -#----------------------------------------------------------------------------- -# -# Test lhu instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 16,0 - li a4,512 - vsetvl a4,a4 - - la a5,src - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsd vx1,a6 - fence - - li a2,0 -loop: - ld a0,0(a6) - ld a1,0(a5) - sll a3,a1,48 - srl a3,a3,48 - addi TESTNUM,a2,2 - bne a0,a3,fail - addi a6,a6,8 - addi a5,a5,8 - addi a2,a2,1 - bne a2,a4,loop - j pass - -vtcode: - utidx x3 - slli x3,x3,3 - add x2,x2,x3 - lhu x1,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src: -#include "data_d.h" - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/lw.S b/isa/rv64uv/lw.S deleted file mode 100644 index 4986984..0000000 --- a/isa/rv64uv/lw.S +++ /dev/null @@ -1,64 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# lw.S -#----------------------------------------------------------------------------- -# -# Test lw instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 16,0 - li a4,512 - vsetvl a4,a4 - - la a5,src - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsd vx1,a6 - fence - - li a2,0 -loop: - ld a0,0(a6) - ld a1,0(a5) - sll a3,a1,32 - sra a3,a3,32 - addi TESTNUM,a2,2 - bne a0,a3,fail - addi a6,a6,8 - addi a5,a5,8 - addi a2,a2,1 - bne a2,a4,loop - j pass - -vtcode: - utidx x3 - slli x3,x3,3 - add x2,x2,x3 - lw x1,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src: -#include "data_d.h" - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/lwu.S b/isa/rv64uv/lwu.S deleted file mode 100644 index 502662a..0000000 --- a/isa/rv64uv/lwu.S +++ /dev/null @@ -1,64 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# lwu.S -#----------------------------------------------------------------------------- -# -# Test lwu instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 16,0 - li a4,512 - vsetvl a4,a4 - - la a5,src - vmsv vx2,a5 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a6,dest - vsd vx1,a6 - fence - - li a2,0 -loop: - ld a0,0(a6) - ld a1,0(a5) - sll a3,a1,32 - srl a3,a3,32 - addi TESTNUM,a2,2 - bne a0,a3,fail - addi a6,a6,8 - addi a5,a5,8 - addi a2,a2,1 - bne a2,a4,loop - j pass - -vtcode: - utidx x3 - slli x3,x3,3 - add x2,x2,x3 - lwu x1,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src: -#include "data_d.h" - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/movn.S b/isa/rv64uv/movn.S deleted file mode 100644 index 97b6261..0000000 --- a/isa/rv64uv/movn.S +++ /dev/null @@ -1,61 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# movn.S -#----------------------------------------------------------------------------- -# -# Test movn instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a6,2048 - vsetvl a6,a6 - - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a7,dest - vsd vx3,a7 - fence - - li a1,0 - li a2,-1 -loop: - ld a0,0(a7) - slt a4,a1,10 - slli a4,a4,63 - srai a4,a4,63 - and a5,a2,a4 - addi s8,a1,2 - bne a0,a5,fail - addi a7,a7,8 - addi a1,a1,1 - bne a1,a6,loop - j pass - -vtcode: - utidx x1 - slti x2,x1,10 - li x1,-1 - li x3,0 - movn x3,x2,x1 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/movz.S b/isa/rv64uv/movz.S deleted file mode 100644 index 8680ac6..0000000 --- a/isa/rv64uv/movz.S +++ /dev/null @@ -1,62 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# movz.S -#----------------------------------------------------------------------------- -# -# Test movz instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 4,0 - li a6,2048 - vsetvl a6,a6 - - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a7,dest - vsd vx3,a7 - fence - - li a1,0 - li a2,-1 -loop: - ld a0,0(a7) - slti a4,a1,10 - slli a4,a4,63 - srai a4,a4,63 - xori a4,a4,-1 - and a5,a2,a4 - addi TESTNUM,a1,2 - bne a0,a5,fail - addi a7,a7,8 - addi a1,a1,1 - bne a1,a6,loop - j pass - -vtcode: - utidx x1 - slti x2,x1,10 - li x1,-1 - li x3,0 - movz x3,x2,x1 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/sb.S b/isa/rv64uv/sb.S deleted file mode 100644 index 645da07..0000000 --- a/isa/rv64uv/sb.S +++ /dev/null @@ -1,74 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# sb.S -#----------------------------------------------------------------------------- -# -# Test sb instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 16,0 - li a4,512 - vsetvl a4,a4 - - la a6,dest - li a2,0 - -initloop: - sd x0,0(a6) - addi a6,a6,8 - addi a2,a2,1 - bne a2,a4,initloop - fence - - la a5,src - vld vx1,a5 - la a6,dest - vmsv vx2,a6 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - fence - - li a2,0 -loop: - ld a0,0(a6) - ld a1,0(a5) - sll a3,a1,56 - srl a3,a3,56 - addi TESTNUM,a2,2 - bne a0,a3,fail - addi a6,a6,8 - addi a5,a5,8 - addi a2,a2,1 - bne a2,a4,loop - j pass - -vtcode: - utidx x3 - slli x3,x3,3 - add x2,x2,x3 - sb x1,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src: -#include "data_d.h" - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/sd.S b/isa/rv64uv/sd.S deleted file mode 100644 index 7fb0e8f..0000000 --- a/isa/rv64uv/sd.S +++ /dev/null @@ -1,62 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# sd.S -#----------------------------------------------------------------------------- -# -# Test sd instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 16,0 - li a4,512 - vsetvl a4,a4 - - la a5,src - vld vx1,a5 - la a6,dest - vmsv vx2,a6 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - fence - - li a2,0 -loop: - ld a0,0(a6) - ld a1,0(a5) - addi TESTNUM,a2,2 - bne a0,a1,fail - addi a6,a6,8 - addi a5,a5,8 - addi a2,a2,1 - bne a2,a4,loop - j pass - -vtcode: - utidx x3 - slli x3,x3,3 - add x2,x2,x3 - sd x1,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src: -#include "data_d.h" - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/sh.S b/isa/rv64uv/sh.S deleted file mode 100644 index c87f070..0000000 --- a/isa/rv64uv/sh.S +++ /dev/null @@ -1,74 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# sh.S -#----------------------------------------------------------------------------- -# -# Test sh instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 16,0 - li a4,512 - vsetvl a4,a4 - - la a6,dest - li a2,0 - -initloop: - sd x0,0(a6) - addi a6,a6,8 - addi a2,a2,1 - bne a2,a4,initloop - fence - - la a5,src - vld vx1,a5 - la a6,dest - vmsv vx2,a6 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - fence - - li a2,0 -loop: - ld a0,0(a6) - ld a1,0(a5) - sll a3,a1,48 - srl a3,a3,48 - addi TESTNUM,a2,2 - bne a0,a3,fail - addi a6,a6,8 - addi a5,a5,8 - addi a2,a2,1 - bne a2,a4,loop - j pass - -vtcode: - utidx x3 - slli x3,x3,3 - add x2,x2,x3 - sh x1,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src: -#include "data_d.h" - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/sw.S b/isa/rv64uv/sw.S deleted file mode 100644 index efad38c..0000000 --- a/isa/rv64uv/sw.S +++ /dev/null @@ -1,74 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# sw.S -#----------------------------------------------------------------------------- -# -# Test sw instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 16,0 - li a4,512 - vsetvl a4,a4 - - la a6,dest - li a2,0 - -initloop: - sd x0,0(a6) - addi a6,a6,8 - addi a2,a2,1 - bne a2,a4,initloop - fence - - la a5,src - vld vx1,a5 - la a6,dest - vmsv vx2,a6 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - fence - - li a2,0 -loop: - ld a0,0(a6) - ld a1,0(a5) - sll a3,a1,32 - srl a3,a3,32 - addi TESTNUM,a2,2 - bne a0,a3,fail - addi a6,a6,8 - addi a5,a5,8 - addi a2,a2,1 - bne a2,a4,loop - j pass - -vtcode: - utidx x3 - slli x3,x3,3 - add x2,x2,x3 - sw x1,0(x2) - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src: -#include "data_d.h" - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/utidx.S b/isa/rv64uv/utidx.S deleted file mode 100644 index 564bf19..0000000 --- a/isa/rv64uv/utidx.S +++ /dev/null @@ -1,53 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# utidx.S -#----------------------------------------------------------------------------- -# -# Test utidx instruction in a vf block. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 2,0 - li a2,2048 - vsetvl a2,a2 - - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a4,dest - vsd vx1,a4 - fence - - li a1,1 -loop: - ld a0,0(a4) - addi TESTNUM,a1,2 - bne a0,a1,fail - addi a4,a4,8 - addi a1,a1,1 - bne a1,a2,loop - j pass - -vtcode: - utidx x1 - addi x1,x1,1 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/vfmsv_d.S b/isa/rv64uv/vfmsv_d.S deleted file mode 100644 index 97a14e3..0000000 --- a/isa/rv64uv/vfmsv_d.S +++ /dev/null @@ -1,57 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# vfmsv_d.S -#----------------------------------------------------------------------------- -# -# Test vfmsv.d instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 3,1 - li a2,680 - vsetvl a2,a2 - - li a3,-1 - vfmsv.d vf0,a3 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a4,dest - vsd vx2,a4 - fence - - li a1,0 -loop: - ld a0,0(a4) - addi TESTNUM,a1,2 - bne a0,a1,fail - addi a4,a4,8 - addi a1,a1,1 - bne a1,a2,loop - j pass - -vtcode: - utidx x1 - addi x1,x1,1 - fmv.x.d x2, f0 - add x2,x1,x2 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/vfmsv_s.S b/isa/rv64uv/vfmsv_s.S deleted file mode 100644 index cf5f881..0000000 --- a/isa/rv64uv/vfmsv_s.S +++ /dev/null @@ -1,57 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# vfmsv_s.S -#----------------------------------------------------------------------------- -# -# Test vfmsv.s instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 3,1 - li a2,680 - vsetvl a2,a2 - - li a3,-1 - vfmsv.s vf0,a3 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a4,dest - vsd vx2,a4 - fence - - li a1,0 -loop: - ld a0,0(a4) - addi TESTNUM,a1,2 - bne a0,a1,fail - addi a4,a4,8 - addi a1,a1,1 - bne a1,a2,loop - j pass - -vtcode: - utidx x1 - addi x1,x1,1 - fmv.x.s x2, f0 - add x2,x1,x2 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/vfmvv.S b/isa/rv64uv/vfmvv.S deleted file mode 100644 index c1acfc4..0000000 --- a/isa/rv64uv/vfmvv.S +++ /dev/null @@ -1,55 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# vfmvv.S -#----------------------------------------------------------------------------- -# -# Test vfmvv instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 2,2 - li a2,2048 - vsetvl a2,a2 - - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - vfmvv vf1,vf0 - la a3,dest - vfsd vf1,a3 - fence - - li a1,1 -loop: - ld a0,0(a3) - addi TESTNUM,a1,2 - bne a0,a1,fail - addi a3,a3,8 - addi a1,a1,1 - bne a1,a2,loop - j pass - -vtcode: - utidx x1 - addi x1,x1,1 - fmv.d.x f0,x1 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/vmsv.S b/isa/rv64uv/vmsv.S deleted file mode 100644 index fe16651..0000000 --- a/isa/rv64uv/vmsv.S +++ /dev/null @@ -1,56 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# vmsv.S -#----------------------------------------------------------------------------- -# -# Test vmsv instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 3,0 - li a2,2048 - vsetvl a2,a2 - - li a3,-1 - vmsv vx2,a3 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a4,dest - vsd vx2,a4 - fence - - li a1,0 -loop: - ld a0,0(a4) - addi TESTNUM,a1,2 - bne a0,a1,fail - addi a4,a4,8 - addi a1,a1,1 - bne a1,a2,loop - j pass - -vtcode: - utidx x1 - addi x1,x1,1 - add x2,x1,x2 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/vmvv.S b/isa/rv64uv/vmvv.S deleted file mode 100644 index c3529f1..0000000 --- a/isa/rv64uv/vmvv.S +++ /dev/null @@ -1,54 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# vmvv.S -#----------------------------------------------------------------------------- -# -# Test vmvv instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 3,0 - li a2,2048 - vsetvl a2,a2 - - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - vmvv vx2,vx1 - la a4,dest - vsd vx2,a4 - fence - - li a1,1 -loop: - ld a0,0(a4) - addi TESTNUM,a1,2 - bne a0,a1,fail - addi a4,a4,8 - addi a1,a1,1 - bne a1,a2,loop - j pass - -vtcode: - utidx x1 - addi x1,x1,1 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -dest: - .skip 16384 - -RVTEST_DATA_END diff --git a/isa/rv64uv/vsetcfg.S b/isa/rv64uv/vsetcfg.S deleted file mode 100644 index 00ff1ac..0000000 --- a/isa/rv64uv/vsetcfg.S +++ /dev/null @@ -1,561 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# vsetcfg.S -#----------------------------------------------------------------------------- -# -# Test vsetcfg instruction without immediates. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - #TEST_VVCFG( 2, 0, 0, 0xf8, 768, 768 ); - #TEST_VVCFG( 3, 0, 0, 0xf8, 769, 768 ); - #TEST_VVCFG( 4, 0, 0, 0xf8, 767, 767 ); - - TEST_VVCFG( 5, 0, 0, 0x00, 2048, 2048 ); - TEST_VVCFG( 6, 0, 0, 0x00, 2049, 2048 ); - TEST_VVCFG( 7, 0, 0, 0x00, 2047, 2047 ); - - #TEST_VVCFG( 8, 1, 0, 0xf8, 768, 768 ); - #TEST_VVCFG( 9, 1, 0, 0xf8, 769, 768 ); - #TEST_VVCFG( 10, 1, 0, 0xf8, 767, 767 ); - - TEST_VVCFG( 11, 1, 0, 0x00, 2048, 2048 ); - TEST_VVCFG( 12, 1, 0, 0x00, 2049, 2048 ); - TEST_VVCFG( 13, 1, 0, 0x00, 2047, 2047 ); - - #TEST_VVCFG( 14, 2, 0, 0xf8, 768, 768 ); - #TEST_VVCFG( 15, 2, 0, 0xf8, 769, 768 ); - #TEST_VVCFG( 16, 2, 0, 0xf8, 767, 767 ); - - TEST_VVCFG( 17, 2, 0, 0x00, 2048, 2048 ); - TEST_VVCFG( 18, 2, 0, 0x00, 2049, 2048 ); - TEST_VVCFG( 19, 2, 0, 0x00, 2047, 2047 ); - - #TEST_VVCFG( 20, 3, 0, 0xf8, 384, 384 ); - #TEST_VVCFG( 21, 3, 0, 0xf8, 385, 384 ); - #TEST_VVCFG( 22, 3, 0, 0xf8, 383, 383 ); - - TEST_VVCFG( 23, 3, 0, 0x00, 1024, 1024 ); - TEST_VVCFG( 24, 3, 0, 0x00, 1025, 1024 ); - TEST_VVCFG( 25, 3, 0, 0x00, 1023, 1023 ); - - #TEST_VVCFG( 26, 4, 0, 0xf8, 255, 255 ); - #TEST_VVCFG( 27, 4, 0, 0xf8, 256, 255 ); - #TEST_VVCFG( 28, 4, 0, 0xf8, 254, 254 ); - - TEST_VVCFG( 29, 4, 0, 0x00, 680, 680 ); - TEST_VVCFG( 30, 4, 0, 0x00, 681, 680 ); - TEST_VVCFG( 31, 4, 0, 0x00, 679, 679 ); - - #TEST_VVCFG( 32, 5, 0, 0xf8, 192, 192 ); - #TEST_VVCFG( 33, 5, 0, 0xf8, 193, 192 ); - #TEST_VVCFG( 34, 5, 0, 0xf8, 191, 191 ); - - TEST_VVCFG( 35, 5, 0, 0x00, 512, 512 ); - TEST_VVCFG( 36, 5, 0, 0x00, 513, 512 ); - TEST_VVCFG( 37, 5, 0, 0x00, 511, 511 ); - - #TEST_VVCFG( 38, 6, 0, 0xf8, 153, 153 ); - #TEST_VVCFG( 39, 6, 0, 0xf8, 154, 153 ); - #TEST_VVCFG( 40, 6, 0, 0xf8, 152, 152 ); - - TEST_VVCFG( 41, 6, 0, 0x00, 408, 408 ); - TEST_VVCFG( 42, 6, 0, 0x00, 409, 408 ); - TEST_VVCFG( 43, 6, 0, 0x00, 407, 407 ); - - #TEST_VVCFG( 44, 7, 0, 0xf8, 126, 126 ); - #TEST_VVCFG( 45, 7, 0, 0xf8, 127, 126 ); - #TEST_VVCFG( 46, 7, 0, 0xf8, 125, 125 ); - - TEST_VVCFG( 47, 7, 0, 0x00, 336, 336 ); - TEST_VVCFG( 48, 7, 0, 0x00, 337, 336 ); - TEST_VVCFG( 49, 7, 0, 0x00, 335, 335 ); - - #TEST_VVCFG( 50, 8, 0, 0xf8, 108, 108 ); - #TEST_VVCFG( 51, 8, 0, 0xf8, 109, 108 ); - #TEST_VVCFG( 52, 8, 0, 0xf8, 107, 107 ); - - TEST_VVCFG( 53, 8, 0, 0x00, 288, 288 ); - TEST_VVCFG( 54, 8, 0, 0x00, 289, 288 ); - TEST_VVCFG( 55, 8, 0, 0x00, 287, 287 ); - - #TEST_VVCFG( 56, 9, 0, 0xf8, 96, 96 ); - #TEST_VVCFG( 57, 9, 0, 0xf8, 97, 96 ); - #TEST_VVCFG( 58, 9, 0, 0xf8, 95, 95 ); - - TEST_VVCFG( 59, 9, 0, 0x00, 256, 256 ); - TEST_VVCFG( 60, 9, 0, 0x00, 257, 256 ); - TEST_VVCFG( 61, 9, 0, 0x00, 255, 255 ); - - #TEST_VVCFG( 62, 10, 0, 0xf8, 84, 84 ); - #TEST_VVCFG( 63, 10, 0, 0xf8, 85, 84 ); - #TEST_VVCFG( 64, 10, 0, 0xf8, 83, 83 ); - - TEST_VVCFG( 65, 10, 0, 0x00, 224, 224 ); - TEST_VVCFG( 66, 10, 0, 0x00, 225, 224 ); - TEST_VVCFG( 67, 10, 0, 0x00, 223, 223 ); - - #TEST_VVCFG( 68, 11, 0, 0xf8, 75, 75 ); - #TEST_VVCFG( 69, 11, 0, 0xf8, 76, 75 ); - #TEST_VVCFG( 70, 11, 0, 0xf8, 74, 74 ); - - TEST_VVCFG( 71, 11, 0, 0x00, 200, 200 ); - TEST_VVCFG( 72, 11, 0, 0x00, 201, 200 ); - TEST_VVCFG( 73, 11, 0, 0x00, 199, 199 ); - - #TEST_VVCFG( 74, 12, 0, 0xf8, 69, 69 ); - #TEST_VVCFG( 75, 12, 0, 0xf8, 70, 69 ); - #TEST_VVCFG( 76, 12, 0, 0xf8, 68, 68 ); - - TEST_VVCFG( 77, 12, 0, 0x00, 184, 184 ); - TEST_VVCFG( 78, 12, 0, 0x00, 185, 184 ); - TEST_VVCFG( 79, 12, 0, 0x00, 183, 183 ); - - #TEST_VVCFG( 80, 13, 0, 0xf8, 63, 63 ); - #TEST_VVCFG( 81, 13, 0, 0xf8, 64, 63 ); - #TEST_VVCFG( 82, 13, 0, 0xf8, 62, 62 ); - - TEST_VVCFG( 83, 13, 0, 0x00, 168, 168 ); - TEST_VVCFG( 84, 13, 0, 0x00, 169, 168 ); - TEST_VVCFG( 85, 13, 0, 0x00, 167, 167 ); - - #TEST_VVCFG( 86, 14, 0, 0xf8, 57, 57 ); - #TEST_VVCFG( 87, 14, 0, 0xf8, 58, 57 ); - #TEST_VVCFG( 88, 14, 0, 0xf8, 56, 56 ); - - TEST_VVCFG( 89, 14, 0, 0x00, 152, 152 ); - TEST_VVCFG( 90, 14, 0, 0x00, 153, 152 ); - TEST_VVCFG( 91, 14, 0, 0x00, 151, 151 ); - - #TEST_VVCFG( 92, 15, 0, 0xf8, 54, 54 ); - #TEST_VVCFG( 93, 15, 0, 0xf8, 55, 54 ); - #TEST_VVCFG( 94, 15, 0, 0xf8, 53, 53 ); - - TEST_VVCFG( 95, 15, 0, 0x00, 144, 144 ); - TEST_VVCFG( 96, 15, 0, 0x00, 145, 144 ); - TEST_VVCFG( 97, 15, 0, 0x00, 143, 143 ); - - #TEST_VVCFG( 98, 16, 0, 0xf8, 51, 51 ); - #TEST_VVCFG( 99, 16, 0, 0xf8, 52, 51 ); - #TEST_VVCFG( 100, 16, 0, 0xf8, 50, 50 ); - - TEST_VVCFG( 101, 16, 0, 0x00, 136, 136 ); - TEST_VVCFG( 102, 16, 0, 0x00, 137, 136 ); - TEST_VVCFG( 103, 16, 0, 0x00, 135, 135 ); - - #TEST_VVCFG( 104, 17, 0, 0xf8, 48, 48 ); - #TEST_VVCFG( 105, 17, 0, 0xf8, 49, 48 ); - #TEST_VVCFG( 106, 17, 0, 0xf8, 47, 47 ); - - TEST_VVCFG( 107, 17, 0, 0x00, 128, 128 ); - TEST_VVCFG( 108, 17, 0, 0x00, 129, 128 ); - TEST_VVCFG( 109, 17, 0, 0x00, 127, 127 ); - - #TEST_VVCFG( 110, 18, 0, 0xf8, 45, 45 ); - #TEST_VVCFG( 111, 18, 0, 0xf8, 46, 45 ); - #TEST_VVCFG( 112, 18, 0, 0xf8, 44, 44 ); - - TEST_VVCFG( 113, 18, 0, 0x00, 120, 120 ); - TEST_VVCFG( 114, 18, 0, 0x00, 121, 120 ); - TEST_VVCFG( 115, 18, 0, 0x00, 119, 119 ); - - #TEST_VVCFG( 116, 19, 0, 0xf8, 42, 42 ); - #TEST_VVCFG( 117, 19, 0, 0xf8, 43, 42 ); - #TEST_VVCFG( 118, 19, 0, 0xf8, 41, 41 ); - - TEST_VVCFG( 119, 19, 0, 0x00, 112, 112 ); - TEST_VVCFG( 120, 19, 0, 0x00, 113, 112 ); - TEST_VVCFG( 121, 19, 0, 0x00, 111, 111 ); - - #TEST_VVCFG( 122, 20, 0, 0xf8, 39, 39 ); - #TEST_VVCFG( 123, 20, 0, 0xf8, 40, 39 ); - #TEST_VVCFG( 124, 20, 0, 0xf8, 38, 38 ); - - TEST_VVCFG( 125, 20, 0, 0x00, 104, 104 ); - TEST_VVCFG( 126, 20, 0, 0x00, 105, 104 ); - TEST_VVCFG( 127, 20, 0, 0x00, 103, 103 ); - - #TEST_VVCFG( 128, 21, 0, 0xf8, 36, 36 ); - #TEST_VVCFG( 129, 21, 0, 0xf8, 37, 36 ); - #TEST_VVCFG( 130, 21, 0, 0xf8, 35, 35 ); - - TEST_VVCFG( 131, 21, 0, 0x00, 96, 96 ); - TEST_VVCFG( 132, 21, 0, 0x00, 97, 96 ); - TEST_VVCFG( 133, 21, 0, 0x00, 95, 95 ); - - #TEST_VVCFG( 134, 22, 0, 0xf8, 36, 36 ); - #TEST_VVCFG( 135, 22, 0, 0xf8, 37, 36 ); - #TEST_VVCFG( 136, 22, 0, 0xf8, 35, 35 ); - - TEST_VVCFG( 137, 22, 0, 0x00, 96, 96 ); - TEST_VVCFG( 138, 22, 0, 0x00, 97, 96 ); - TEST_VVCFG( 139, 22, 0, 0x00, 95, 95 ); - - #TEST_VVCFG( 140, 23, 0, 0xf8, 33, 33 ); - #TEST_VVCFG( 141, 23, 0, 0xf8, 34, 33 ); - #TEST_VVCFG( 142, 23, 0, 0xf8, 32, 32 ); - - TEST_VVCFG( 143, 23, 0, 0x00, 88, 88 ); - TEST_VVCFG( 144, 23, 0, 0x00, 89, 88 ); - TEST_VVCFG( 145, 23, 0, 0x00, 87, 87 ); - - #TEST_VVCFG( 146, 24, 0, 0xf8, 33, 33 ); - #TEST_VVCFG( 147, 24, 0, 0xf8, 34, 33 ); - #TEST_VVCFG( 148, 24, 0, 0xf8, 32, 32 ); - - TEST_VVCFG( 149, 24, 0, 0x00, 88, 88 ); - TEST_VVCFG( 150, 24, 0, 0x00, 89, 88 ); - TEST_VVCFG( 151, 24, 0, 0x00, 87, 87 ); - - #TEST_VVCFG( 152, 25, 0, 0xf8, 30, 30 ); - #TEST_VVCFG( 153, 25, 0, 0xf8, 31, 30 ); - #TEST_VVCFG( 154, 25, 0, 0xf8, 29, 29 ); - - TEST_VVCFG( 155, 25, 0, 0x00, 80, 80 ); - TEST_VVCFG( 156, 25, 0, 0x00, 81, 80 ); - TEST_VVCFG( 157, 25, 0, 0x00, 79, 79 ); - - #TEST_VVCFG( 158, 26, 0, 0xf8, 30, 30 ); - #TEST_VVCFG( 159, 26, 0, 0xf8, 31, 30 ); - #TEST_VVCFG( 160, 26, 0, 0xf8, 29, 29 ); - - TEST_VVCFG( 161, 26, 0, 0x00, 80, 80 ); - TEST_VVCFG( 162, 26, 0, 0x00, 81, 80 ); - TEST_VVCFG( 163, 26, 0, 0x00, 79, 79 ); - - #TEST_VVCFG( 164, 27, 0, 0xf8, 27, 27 ); - #TEST_VVCFG( 165, 27, 0, 0xf8, 28, 27 ); - #TEST_VVCFG( 166, 27, 0, 0xf8, 26, 26 ); - - TEST_VVCFG( 167, 27, 0, 0x00, 72, 72 ); - TEST_VVCFG( 168, 27, 0, 0x00, 73, 72 ); - TEST_VVCFG( 169, 27, 0, 0x00, 71, 71 ); - - #TEST_VVCFG( 170, 28, 0, 0xf8, 27, 27 ); - #TEST_VVCFG( 171, 28, 0, 0xf8, 28, 27 ); - #TEST_VVCFG( 172, 28, 0, 0xf8, 26, 26 ); - - TEST_VVCFG( 173, 28, 0, 0x00, 72, 72 ); - TEST_VVCFG( 174, 28, 0, 0x00, 73, 72 ); - TEST_VVCFG( 175, 28, 0, 0x00, 71, 71 ); - - #TEST_VVCFG( 176, 29, 0, 0xf8, 27, 27 ); - #TEST_VVCFG( 177, 29, 0, 0xf8, 28, 27 ); - #TEST_VVCFG( 178, 29, 0, 0xf8, 26, 26 ); - - TEST_VVCFG( 179, 29, 0, 0x00, 72, 72 ); - TEST_VVCFG( 180, 29, 0, 0x00, 73, 72 ); - TEST_VVCFG( 181, 29, 0, 0x00, 71, 71 ); - - #TEST_VVCFG( 182, 30, 0, 0xf8, 24, 24 ); - #TEST_VVCFG( 183, 30, 0, 0xf8, 25, 24 ); - #TEST_VVCFG( 184, 30, 0, 0xf8, 23, 23 ); - - TEST_VVCFG( 185, 30, 0, 0x00, 64, 64 ); - TEST_VVCFG( 186, 30, 0, 0x00, 65, 64 ); - TEST_VVCFG( 187, 30, 0, 0x00, 63, 63 ); - - #TEST_VVCFG( 188, 31, 0, 0xf8, 24, 24 ); - #TEST_VVCFG( 189, 31, 0, 0xf8, 25, 24 ); - #TEST_VVCFG( 190, 31, 0, 0xf8, 23, 23 ); - - TEST_VVCFG( 191, 31, 0, 0x00, 64, 64 ); - TEST_VVCFG( 192, 31, 0, 0x00, 65, 64 ); - TEST_VVCFG( 193, 31, 0, 0x00, 63, 63 ); - - #TEST_VVCFG( 194, 32, 0, 0xf8, 24, 24 ); - #TEST_VVCFG( 195, 32, 0, 0xf8, 25, 24 ); - #TEST_VVCFG( 196, 32, 0, 0xf8, 23, 23 ); - - TEST_VVCFG( 197, 32, 0, 0x00, 64, 64 ); - TEST_VVCFG( 198, 32, 0, 0x00, 65, 64 ); - TEST_VVCFG( 199, 32, 0, 0x00, 63, 63 ); - - #TEST_VVCFG( 200, 32, 0, 0xf8, 24, 24 ); - #TEST_VVCFG( 201, 32, 0, 0xf8, 25, 24 ); - #TEST_VVCFG( 202, 32, 0, 0xf8, 23, 23 ); - - TEST_VVCFG( 203, 32, 0, 0x00, 64, 64 ); - TEST_VVCFG( 204, 32, 0, 0x00, 65, 64 ); - TEST_VVCFG( 205, 32, 0, 0x00, 63, 63 ); - - #TEST_VVCFG( 206, 32, 1, 0xf8, 24, 24 ); - #TEST_VVCFG( 207, 32, 1, 0xf8, 25, 24 ); - #TEST_VVCFG( 208, 32, 1, 0xf8, 23, 23 ); - - TEST_VVCFG( 209, 32, 1, 0x00, 64, 64 ); - TEST_VVCFG( 210, 32, 1, 0x00, 65, 64 ); - TEST_VVCFG( 211, 32, 1, 0x00, 63, 63 ); - - #TEST_VVCFG( 212, 32, 2, 0xf8, 21, 21 ); - #TEST_VVCFG( 213, 32, 2, 0xf8, 22, 21 ); - #TEST_VVCFG( 214, 32, 2, 0xf8, 20, 20 ); - - TEST_VVCFG( 215, 32, 2, 0x00, 56, 56 ); - TEST_VVCFG( 216, 32, 2, 0x00, 57, 56 ); - TEST_VVCFG( 217, 32, 2, 0x00, 55, 55 ); - - #TEST_VVCFG( 218, 32, 3, 0xf8, 21, 21 ); - #TEST_VVCFG( 219, 32, 3, 0xf8, 22, 21 ); - #TEST_VVCFG( 220, 32, 3, 0xf8, 20, 20 ); - - TEST_VVCFG( 221, 32, 3, 0x00, 56, 56 ); - TEST_VVCFG( 222, 32, 3, 0x00, 57, 56 ); - TEST_VVCFG( 223, 32, 3, 0x00, 55, 55 ); - - #TEST_VVCFG( 224, 32, 4, 0xf8, 21, 21 ); - #TEST_VVCFG( 225, 32, 4, 0xf8, 22, 21 ); - #TEST_VVCFG( 226, 32, 4, 0xf8, 20, 20 ); - - TEST_VVCFG( 227, 32, 4, 0x00, 56, 56 ); - TEST_VVCFG( 228, 32, 4, 0x00, 57, 56 ); - TEST_VVCFG( 229, 32, 4, 0x00, 55, 55 ); - - #TEST_VVCFG( 230, 32, 5, 0xf8, 21, 21 ); - #TEST_VVCFG( 231, 32, 5, 0xf8, 22, 21 ); - #TEST_VVCFG( 232, 32, 5, 0xf8, 20, 20 ); - - TEST_VVCFG( 233, 32, 5, 0x00, 56, 56 ); - TEST_VVCFG( 234, 32, 5, 0x00, 57, 56 ); - TEST_VVCFG( 235, 32, 5, 0x00, 55, 55 ); - - #TEST_VVCFG( 236, 32, 6, 0xf8, 18, 18 ); - #TEST_VVCFG( 237, 32, 6, 0xf8, 19, 18 ); - #TEST_VVCFG( 238, 32, 6, 0xf8, 17, 17 ); - - TEST_VVCFG( 239, 32, 6, 0x00, 48, 48 ); - TEST_VVCFG( 240, 32, 6, 0x00, 49, 48 ); - TEST_VVCFG( 241, 32, 6, 0x00, 47, 47 ); - - #TEST_VVCFG( 242, 32, 7, 0xf8, 18, 18 ); - #TEST_VVCFG( 243, 32, 7, 0xf8, 19, 18 ); - #TEST_VVCFG( 244, 32, 7, 0xf8, 17, 17 ); - - TEST_VVCFG( 245, 32, 7, 0x00, 48, 48 ); - TEST_VVCFG( 246, 32, 7, 0x00, 49, 48 ); - TEST_VVCFG( 247, 32, 7, 0x00, 47, 47 ); - - #TEST_VVCFG( 248, 32, 8, 0xf8, 18, 18 ); - #TEST_VVCFG( 249, 32, 8, 0xf8, 19, 18 ); - #TEST_VVCFG( 250, 32, 8, 0xf8, 17, 17 ); - - TEST_VVCFG( 251, 32, 8, 0x00, 48, 48 ); - TEST_VVCFG( 252, 32, 8, 0x00, 49, 48 ); - TEST_VVCFG( 253, 32, 8, 0x00, 47, 47 ); - - #TEST_VVCFG( 254, 32, 9, 0xf8, 18, 18 ); - #TEST_VVCFG( 255, 32, 9, 0xf8, 19, 18 ); - #TEST_VVCFG( 256, 32, 9, 0xf8, 17, 17 ); - - TEST_VVCFG( 257, 32, 9, 0x00, 48, 48 ); - TEST_VVCFG( 258, 32, 9, 0x00, 49, 48 ); - TEST_VVCFG( 259, 32, 9, 0x00, 47, 47 ); - - #TEST_VVCFG( 260, 32, 10, 0xf8, 18, 18 ); - #TEST_VVCFG( 261, 32, 10, 0xf8, 19, 18 ); - #TEST_VVCFG( 262, 32, 10, 0xf8, 17, 17 ); - - TEST_VVCFG( 263, 32, 10, 0x00, 48, 48 ); - TEST_VVCFG( 264, 32, 10, 0x00, 49, 48 ); - TEST_VVCFG( 265, 32, 10, 0x00, 47, 47 ); - - #TEST_VVCFG( 266, 32, 11, 0xf8, 18, 18 ); - #TEST_VVCFG( 267, 32, 11, 0xf8, 19, 18 ); - #TEST_VVCFG( 268, 32, 11, 0xf8, 17, 17 ); - - TEST_VVCFG( 269, 32, 11, 0x00, 48, 48 ); - TEST_VVCFG( 270, 32, 11, 0x00, 49, 48 ); - TEST_VVCFG( 271, 32, 11, 0x00, 47, 47 ); - - #TEST_VVCFG( 272, 32, 12, 0xf8, 15, 15 ); - #TEST_VVCFG( 273, 32, 12, 0xf8, 16, 15 ); - #TEST_VVCFG( 274, 32, 12, 0xf8, 14, 14 ); - - TEST_VVCFG( 275, 32, 12, 0x00, 40, 40 ); - TEST_VVCFG( 276, 32, 12, 0x00, 41, 40 ); - TEST_VVCFG( 277, 32, 12, 0x00, 39, 39 ); - - #TEST_VVCFG( 278, 32, 13, 0xf8, 15, 15 ); - #TEST_VVCFG( 279, 32, 13, 0xf8, 16, 15 ); - #TEST_VVCFG( 280, 32, 13, 0xf8, 14, 14 ); - - TEST_VVCFG( 281, 32, 13, 0x00, 40, 40 ); - TEST_VVCFG( 282, 32, 13, 0x00, 41, 40 ); - TEST_VVCFG( 283, 32, 13, 0x00, 39, 39 ); - - #TEST_VVCFG( 284, 32, 14, 0xf8, 15, 15 ); - #TEST_VVCFG( 285, 32, 14, 0xf8, 16, 15 ); - #TEST_VVCFG( 286, 32, 14, 0xf8, 14, 14 ); - - TEST_VVCFG( 287, 32, 14, 0x00, 40, 40 ); - TEST_VVCFG( 288, 32, 14, 0x00, 41, 40 ); - TEST_VVCFG( 289, 32, 14, 0x00, 39, 39 ); - - #TEST_VVCFG( 290, 32, 15, 0xf8, 15, 15 ); - #TEST_VVCFG( 291, 32, 15, 0xf8, 16, 15 ); - #TEST_VVCFG( 292, 32, 15, 0xf8, 14, 14 ); - - TEST_VVCFG( 293, 32, 15, 0x00, 40, 40 ); - TEST_VVCFG( 294, 32, 15, 0x00, 41, 40 ); - TEST_VVCFG( 295, 32, 15, 0x00, 39, 39 ); - - #TEST_VVCFG( 296, 32, 16, 0xf8, 15, 15 ); - #TEST_VVCFG( 297, 32, 16, 0xf8, 16, 15 ); - #TEST_VVCFG( 298, 32, 16, 0xf8, 14, 14 ); - - TEST_VVCFG( 299, 32, 16, 0x00, 40, 40 ); - TEST_VVCFG( 300, 32, 16, 0x00, 41, 40 ); - TEST_VVCFG( 301, 32, 16, 0x00, 39, 39 ); - - #TEST_VVCFG( 302, 32, 17, 0xf8, 15, 15 ); - #TEST_VVCFG( 303, 32, 17, 0xf8, 16, 15 ); - #TEST_VVCFG( 304, 32, 17, 0xf8, 14, 14 ); - - TEST_VVCFG( 305, 32, 17, 0x00, 40, 40 ); - TEST_VVCFG( 306, 32, 17, 0x00, 41, 40 ); - TEST_VVCFG( 307, 32, 17, 0x00, 39, 39 ); - - #TEST_VVCFG( 308, 32, 18, 0xf8, 15, 15 ); - #TEST_VVCFG( 309, 32, 18, 0xf8, 16, 15 ); - #TEST_VVCFG( 310, 32, 18, 0xf8, 14, 14 ); - - TEST_VVCFG( 311, 32, 18, 0x00, 40, 40 ); - TEST_VVCFG( 312, 32, 18, 0x00, 41, 40 ); - TEST_VVCFG( 313, 32, 18, 0x00, 39, 39 ); - - #TEST_VVCFG( 314, 32, 19, 0xf8, 15, 15 ); - #TEST_VVCFG( 315, 32, 19, 0xf8, 16, 15 ); - #TEST_VVCFG( 316, 32, 19, 0xf8, 14, 14 ); - - TEST_VVCFG( 317, 32, 19, 0x00, 40, 40 ); - TEST_VVCFG( 318, 32, 19, 0x00, 41, 40 ); - TEST_VVCFG( 319, 32, 19, 0x00, 39, 39 ); - - #TEST_VVCFG( 320, 32, 20, 0xf8, 15, 15 ); - #TEST_VVCFG( 321, 32, 20, 0xf8, 16, 15 ); - #TEST_VVCFG( 322, 32, 20, 0xf8, 14, 14 ); - - TEST_VVCFG( 323, 32, 20, 0x00, 40, 40 ); - TEST_VVCFG( 324, 32, 20, 0x00, 41, 40 ); - TEST_VVCFG( 325, 32, 20, 0x00, 39, 39 ); - - #TEST_VVCFG( 326, 32, 21, 0xf8, 12, 12 ); - #TEST_VVCFG( 327, 32, 21, 0xf8, 13, 12 ); - #TEST_VVCFG( 328, 32, 21, 0xf8, 11, 11 ); - - TEST_VVCFG( 329, 32, 21, 0x00, 32, 32 ); - TEST_VVCFG( 330, 32, 21, 0x00, 33, 32 ); - TEST_VVCFG( 331, 32, 21, 0x00, 31, 31 ); - - #TEST_VVCFG( 332, 32, 22, 0xf8, 12, 12 ); - #TEST_VVCFG( 333, 32, 22, 0xf8, 13, 12 ); - #TEST_VVCFG( 334, 32, 22, 0xf8, 11, 11 ); - - TEST_VVCFG( 335, 32, 22, 0x00, 32, 32 ); - TEST_VVCFG( 336, 32, 22, 0x00, 33, 32 ); - TEST_VVCFG( 337, 32, 22, 0x00, 31, 31 ); - - #TEST_VVCFG( 338, 32, 23, 0xf8, 12, 12 ); - #TEST_VVCFG( 339, 32, 23, 0xf8, 13, 12 ); - #TEST_VVCFG( 340, 32, 23, 0xf8, 11, 11 ); - - TEST_VVCFG( 341, 32, 23, 0x00, 32, 32 ); - TEST_VVCFG( 342, 32, 23, 0x00, 33, 32 ); - TEST_VVCFG( 343, 32, 23, 0x00, 31, 31 ); - - #TEST_VVCFG( 344, 32, 24, 0xf8, 12, 12 ); - #TEST_VVCFG( 345, 32, 24, 0xf8, 13, 12 ); - #TEST_VVCFG( 346, 32, 24, 0xf8, 11, 11 ); - - TEST_VVCFG( 347, 32, 24, 0x00, 32, 32 ); - TEST_VVCFG( 348, 32, 24, 0x00, 33, 32 ); - TEST_VVCFG( 349, 32, 24, 0x00, 31, 31 ); - - #TEST_VVCFG( 350, 32, 25, 0xf8, 12, 12 ); - #TEST_VVCFG( 351, 32, 25, 0xf8, 13, 12 ); - #TEST_VVCFG( 352, 32, 25, 0xf8, 11, 11 ); - - TEST_VVCFG( 353, 32, 25, 0x00, 32, 32 ); - TEST_VVCFG( 354, 32, 25, 0x00, 33, 32 ); - TEST_VVCFG( 355, 32, 25, 0x00, 31, 31 ); - - #TEST_VVCFG( 356, 32, 26, 0xf8, 12, 12 ); - #TEST_VVCFG( 357, 32, 26, 0xf8, 13, 12 ); - #TEST_VVCFG( 358, 32, 26, 0xf8, 11, 11 ); - - TEST_VVCFG( 359, 32, 26, 0x00, 32, 32 ); - TEST_VVCFG( 360, 32, 26, 0x00, 33, 32 ); - TEST_VVCFG( 361, 32, 26, 0x00, 31, 31 ); - - #TEST_VVCFG( 362, 32, 27, 0xf8, 12, 12 ); - #TEST_VVCFG( 363, 32, 27, 0xf8, 13, 12 ); - #TEST_VVCFG( 364, 32, 27, 0xf8, 11, 11 ); - - TEST_VVCFG( 365, 32, 27, 0x00, 32, 32 ); - TEST_VVCFG( 366, 32, 27, 0x00, 33, 32 ); - TEST_VVCFG( 367, 32, 27, 0x00, 31, 31 ); - - #TEST_VVCFG( 368, 32, 28, 0xf8, 12, 12 ); - #TEST_VVCFG( 369, 32, 28, 0xf8, 13, 12 ); - #TEST_VVCFG( 370, 32, 28, 0xf8, 11, 11 ); - - TEST_VVCFG( 371, 32, 28, 0x00, 32, 32 ); - TEST_VVCFG( 372, 32, 28, 0x00, 33, 32 ); - TEST_VVCFG( 373, 32, 28, 0x00, 31, 31 ); - - #TEST_VVCFG( 374, 32, 29, 0xf8, 12, 12 ); - #TEST_VVCFG( 375, 32, 29, 0xf8, 13, 12 ); - #TEST_VVCFG( 376, 32, 29, 0xf8, 11, 11 ); - - TEST_VVCFG( 377, 32, 29, 0x00, 32, 32 ); - TEST_VVCFG( 378, 32, 29, 0x00, 33, 32 ); - TEST_VVCFG( 379, 32, 29, 0x00, 31, 31 ); - - #TEST_VVCFG( 380, 32, 30, 0xf8, 12, 12 ); - #TEST_VVCFG( 381, 32, 30, 0xf8, 13, 12 ); - #TEST_VVCFG( 382, 32, 30, 0xf8, 11, 11 ); - - TEST_VVCFG( 383, 32, 30, 0x00, 32, 32 ); - TEST_VVCFG( 384, 32, 30, 0x00, 33, 32 ); - TEST_VVCFG( 385, 32, 30, 0x00, 31, 31 ); - - #TEST_VVCFG( 386, 32, 31, 0xf8, 12, 12 ); - #TEST_VVCFG( 387, 32, 31, 0xf8, 13, 12 ); - #TEST_VVCFG( 388, 32, 31, 0xf8, 11, 11 ); - - TEST_VVCFG( 389, 32, 31, 0x00, 32, 32 ); - TEST_VVCFG( 390, 32, 31, 0x00, 33, 32 ); - TEST_VVCFG( 391, 32, 31, 0x00, 31, 31 ); - - #TEST_VVCFG( 392, 32, 32, 0xf8, 12, 12 ); - #TEST_VVCFG( 393, 32, 32, 0xf8, 13, 12 ); - #TEST_VVCFG( 394, 32, 32, 0xf8, 11, 11 ); - - TEST_VVCFG( 395, 32, 32, 0x00, 32, 32 ); - TEST_VVCFG( 396, 32, 32, 0x00, 33, 32 ); - TEST_VVCFG( 397, 32, 32, 0x00, 31, 31 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64uv/vsetcfgi.S b/isa/rv64uv/vsetcfgi.S deleted file mode 100644 index bb9a9cc..0000000 --- a/isa/rv64uv/vsetcfgi.S +++ /dev/null @@ -1,561 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# vsetcfgi.S -#----------------------------------------------------------------------------- -# -# Test vsetcfg instruction with immediates. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - #TEST_VSETCFGIVL( 2, 0, 0, 0xf8, 768, 768 ); - #TEST_VSETCFGIVL( 3, 0, 0, 0xf8, 769, 768 ); - #TEST_VSETCFGIVL( 4, 0, 0, 0xf8, 767, 767 ); - - TEST_VSETCFGIVL( 5, 0, 0, 0x00, 2048, 2048 ); - TEST_VSETCFGIVL( 6, 0, 0, 0x00, 2049, 2048 ); - TEST_VSETCFGIVL( 7, 0, 0, 0x00, 2047, 2047 ); - - #TEST_VSETCFGIVL( 8, 1, 0, 0xf8, 768, 768 ); - #TEST_VSETCFGIVL( 9, 1, 0, 0xf8, 769, 768 ); - #TEST_VSETCFGIVL( 10, 1, 0, 0xf8, 767, 767 ); - - TEST_VSETCFGIVL( 11, 1, 0, 0x00, 2048, 2048 ); - TEST_VSETCFGIVL( 12, 1, 0, 0x00, 2049, 2048 ); - TEST_VSETCFGIVL( 13, 1, 0, 0x00, 2047, 2047 ); - - #TEST_VSETCFGIVL( 14, 2, 0, 0xf8, 768, 768 ); - #TEST_VSETCFGIVL( 15, 2, 0, 0xf8, 769, 768 ); - #TEST_VSETCFGIVL( 16, 2, 0, 0xf8, 767, 767 ); - - TEST_VSETCFGIVL( 17, 2, 0, 0x00, 2048, 2048 ); - TEST_VSETCFGIVL( 18, 2, 0, 0x00, 2049, 2048 ); - TEST_VSETCFGIVL( 19, 2, 0, 0x00, 2047, 2047 ); - - #TEST_VSETCFGIVL( 20, 3, 0, 0xf8, 384, 384 ); - #TEST_VSETCFGIVL( 21, 3, 0, 0xf8, 385, 384 ); - #TEST_VSETCFGIVL( 22, 3, 0, 0xf8, 383, 383 ); - - TEST_VSETCFGIVL( 23, 3, 0, 0x00, 1024, 1024 ); - TEST_VSETCFGIVL( 24, 3, 0, 0x00, 1025, 1024 ); - TEST_VSETCFGIVL( 25, 3, 0, 0x00, 1023, 1023 ); - - #TEST_VSETCFGIVL( 26, 4, 0, 0xf8, 255, 255 ); - #TEST_VSETCFGIVL( 27, 4, 0, 0xf8, 256, 255 ); - #TEST_VSETCFGIVL( 28, 4, 0, 0xf8, 254, 254 ); - - TEST_VSETCFGIVL( 29, 4, 0, 0x00, 680, 680 ); - TEST_VSETCFGIVL( 30, 4, 0, 0x00, 681, 680 ); - TEST_VSETCFGIVL( 31, 4, 0, 0x00, 679, 679 ); - - #TEST_VSETCFGIVL( 32, 5, 0, 0xf8, 192, 192 ); - #TEST_VSETCFGIVL( 33, 5, 0, 0xf8, 193, 192 ); - #TEST_VSETCFGIVL( 34, 5, 0, 0xf8, 191, 191 ); - - TEST_VSETCFGIVL( 35, 5, 0, 0x00, 512, 512 ); - TEST_VSETCFGIVL( 36, 5, 0, 0x00, 513, 512 ); - TEST_VSETCFGIVL( 37, 5, 0, 0x00, 511, 511 ); - - #TEST_VSETCFGIVL( 38, 6, 0, 0xf8, 153, 153 ); - #TEST_VSETCFGIVL( 39, 6, 0, 0xf8, 154, 153 ); - #TEST_VSETCFGIVL( 40, 6, 0, 0xf8, 152, 152 ); - - TEST_VSETCFGIVL( 41, 6, 0, 0x00, 408, 408 ); - TEST_VSETCFGIVL( 42, 6, 0, 0x00, 409, 408 ); - TEST_VSETCFGIVL( 43, 6, 0, 0x00, 407, 407 ); - - #TEST_VSETCFGIVL( 44, 7, 0, 0xf8, 126, 126 ); - #TEST_VSETCFGIVL( 45, 7, 0, 0xf8, 127, 126 ); - #TEST_VSETCFGIVL( 46, 7, 0, 0xf8, 125, 125 ); - - TEST_VSETCFGIVL( 47, 7, 0, 0x00, 336, 336 ); - TEST_VSETCFGIVL( 48, 7, 0, 0x00, 337, 336 ); - TEST_VSETCFGIVL( 49, 7, 0, 0x00, 335, 335 ); - - #TEST_VSETCFGIVL( 50, 8, 0, 0xf8, 108, 108 ); - #TEST_VSETCFGIVL( 51, 8, 0, 0xf8, 109, 108 ); - #TEST_VSETCFGIVL( 52, 8, 0, 0xf8, 107, 107 ); - - TEST_VSETCFGIVL( 53, 8, 0, 0x00, 288, 288 ); - TEST_VSETCFGIVL( 54, 8, 0, 0x00, 289, 288 ); - TEST_VSETCFGIVL( 55, 8, 0, 0x00, 287, 287 ); - - #TEST_VSETCFGIVL( 56, 9, 0, 0xf8, 96, 96 ); - #TEST_VSETCFGIVL( 57, 9, 0, 0xf8, 97, 96 ); - #TEST_VSETCFGIVL( 58, 9, 0, 0xf8, 95, 95 ); - - TEST_VSETCFGIVL( 59, 9, 0, 0x00, 256, 256 ); - TEST_VSETCFGIVL( 60, 9, 0, 0x00, 257, 256 ); - TEST_VSETCFGIVL( 61, 9, 0, 0x00, 255, 255 ); - - #TEST_VSETCFGIVL( 62, 10, 0, 0xf8, 84, 84 ); - #TEST_VSETCFGIVL( 63, 10, 0, 0xf8, 85, 84 ); - #TEST_VSETCFGIVL( 64, 10, 0, 0xf8, 83, 83 ); - - TEST_VSETCFGIVL( 65, 10, 0, 0x00, 224, 224 ); - TEST_VSETCFGIVL( 66, 10, 0, 0x00, 225, 224 ); - TEST_VSETCFGIVL( 67, 10, 0, 0x00, 223, 223 ); - - #TEST_VSETCFGIVL( 68, 11, 0, 0xf8, 75, 75 ); - #TEST_VSETCFGIVL( 69, 11, 0, 0xf8, 76, 75 ); - #TEST_VSETCFGIVL( 70, 11, 0, 0xf8, 74, 74 ); - - TEST_VSETCFGIVL( 71, 11, 0, 0x00, 200, 200 ); - TEST_VSETCFGIVL( 72, 11, 0, 0x00, 201, 200 ); - TEST_VSETCFGIVL( 73, 11, 0, 0x00, 199, 199 ); - - #TEST_VSETCFGIVL( 74, 12, 0, 0xf8, 69, 69 ); - #TEST_VSETCFGIVL( 75, 12, 0, 0xf8, 70, 69 ); - #TEST_VSETCFGIVL( 76, 12, 0, 0xf8, 68, 68 ); - - TEST_VSETCFGIVL( 77, 12, 0, 0x00, 184, 184 ); - TEST_VSETCFGIVL( 78, 12, 0, 0x00, 185, 184 ); - TEST_VSETCFGIVL( 79, 12, 0, 0x00, 183, 183 ); - - #TEST_VSETCFGIVL( 80, 13, 0, 0xf8, 63, 63 ); - #TEST_VSETCFGIVL( 81, 13, 0, 0xf8, 64, 63 ); - #TEST_VSETCFGIVL( 82, 13, 0, 0xf8, 62, 62 ); - - TEST_VSETCFGIVL( 83, 13, 0, 0x00, 168, 168 ); - TEST_VSETCFGIVL( 84, 13, 0, 0x00, 169, 168 ); - TEST_VSETCFGIVL( 85, 13, 0, 0x00, 167, 167 ); - - #TEST_VSETCFGIVL( 86, 14, 0, 0xf8, 57, 57 ); - #TEST_VSETCFGIVL( 87, 14, 0, 0xf8, 58, 57 ); - #TEST_VSETCFGIVL( 88, 14, 0, 0xf8, 56, 56 ); - - TEST_VSETCFGIVL( 89, 14, 0, 0x00, 152, 152 ); - TEST_VSETCFGIVL( 90, 14, 0, 0x00, 153, 152 ); - TEST_VSETCFGIVL( 91, 14, 0, 0x00, 151, 151 ); - - #TEST_VSETCFGIVL( 92, 15, 0, 0xf8, 54, 54 ); - #TEST_VSETCFGIVL( 93, 15, 0, 0xf8, 55, 54 ); - #TEST_VSETCFGIVL( 94, 15, 0, 0xf8, 53, 53 ); - - TEST_VSETCFGIVL( 95, 15, 0, 0x00, 144, 144 ); - TEST_VSETCFGIVL( 96, 15, 0, 0x00, 145, 144 ); - TEST_VSETCFGIVL( 97, 15, 0, 0x00, 143, 143 ); - - #TEST_VSETCFGIVL( 98, 16, 0, 0xf8, 51, 51 ); - #TEST_VSETCFGIVL( 99, 16, 0, 0xf8, 52, 51 ); - #TEST_VSETCFGIVL( 100, 16, 0, 0xf8, 50, 50 ); - - TEST_VSETCFGIVL( 101, 16, 0, 0x00, 136, 136 ); - TEST_VSETCFGIVL( 102, 16, 0, 0x00, 137, 136 ); - TEST_VSETCFGIVL( 103, 16, 0, 0x00, 135, 135 ); - - #TEST_VSETCFGIVL( 104, 17, 0, 0xf8, 48, 48 ); - #TEST_VSETCFGIVL( 105, 17, 0, 0xf8, 49, 48 ); - #TEST_VSETCFGIVL( 106, 17, 0, 0xf8, 47, 47 ); - - TEST_VSETCFGIVL( 107, 17, 0, 0x00, 128, 128 ); - TEST_VSETCFGIVL( 108, 17, 0, 0x00, 129, 128 ); - TEST_VSETCFGIVL( 109, 17, 0, 0x00, 127, 127 ); - - #TEST_VSETCFGIVL( 110, 18, 0, 0xf8, 45, 45 ); - #TEST_VSETCFGIVL( 111, 18, 0, 0xf8, 46, 45 ); - #TEST_VSETCFGIVL( 112, 18, 0, 0xf8, 44, 44 ); - - TEST_VSETCFGIVL( 113, 18, 0, 0x00, 120, 120 ); - TEST_VSETCFGIVL( 114, 18, 0, 0x00, 121, 120 ); - TEST_VSETCFGIVL( 115, 18, 0, 0x00, 119, 119 ); - - #TEST_VSETCFGIVL( 116, 19, 0, 0xf8, 42, 42 ); - #TEST_VSETCFGIVL( 117, 19, 0, 0xf8, 43, 42 ); - #TEST_VSETCFGIVL( 118, 19, 0, 0xf8, 41, 41 ); - - TEST_VSETCFGIVL( 119, 19, 0, 0x00, 112, 112 ); - TEST_VSETCFGIVL( 120, 19, 0, 0x00, 113, 112 ); - TEST_VSETCFGIVL( 121, 19, 0, 0x00, 111, 111 ); - - #TEST_VSETCFGIVL( 122, 20, 0, 0xf8, 39, 39 ); - #TEST_VSETCFGIVL( 123, 20, 0, 0xf8, 40, 39 ); - #TEST_VSETCFGIVL( 124, 20, 0, 0xf8, 38, 38 ); - - TEST_VSETCFGIVL( 125, 20, 0, 0x00, 104, 104 ); - TEST_VSETCFGIVL( 126, 20, 0, 0x00, 105, 104 ); - TEST_VSETCFGIVL( 127, 20, 0, 0x00, 103, 103 ); - - #TEST_VSETCFGIVL( 128, 21, 0, 0xf8, 36, 36 ); - #TEST_VSETCFGIVL( 129, 21, 0, 0xf8, 37, 36 ); - #TEST_VSETCFGIVL( 130, 21, 0, 0xf8, 35, 35 ); - - TEST_VSETCFGIVL( 131, 21, 0, 0x00, 96, 96 ); - TEST_VSETCFGIVL( 132, 21, 0, 0x00, 97, 96 ); - TEST_VSETCFGIVL( 133, 21, 0, 0x00, 95, 95 ); - - #TEST_VSETCFGIVL( 134, 22, 0, 0xf8, 36, 36 ); - #TEST_VSETCFGIVL( 135, 22, 0, 0xf8, 37, 36 ); - #TEST_VSETCFGIVL( 136, 22, 0, 0xf8, 35, 35 ); - - TEST_VSETCFGIVL( 137, 22, 0, 0x00, 96, 96 ); - TEST_VSETCFGIVL( 138, 22, 0, 0x00, 97, 96 ); - TEST_VSETCFGIVL( 139, 22, 0, 0x00, 95, 95 ); - - #TEST_VSETCFGIVL( 140, 23, 0, 0xf8, 33, 33 ); - #TEST_VSETCFGIVL( 141, 23, 0, 0xf8, 34, 33 ); - #TEST_VSETCFGIVL( 142, 23, 0, 0xf8, 32, 32 ); - - TEST_VSETCFGIVL( 143, 23, 0, 0x00, 88, 88 ); - TEST_VSETCFGIVL( 144, 23, 0, 0x00, 89, 88 ); - TEST_VSETCFGIVL( 145, 23, 0, 0x00, 87, 87 ); - - #TEST_VSETCFGIVL( 146, 24, 0, 0xf8, 33, 33 ); - #TEST_VSETCFGIVL( 147, 24, 0, 0xf8, 34, 33 ); - #TEST_VSETCFGIVL( 148, 24, 0, 0xf8, 32, 32 ); - - TEST_VSETCFGIVL( 149, 24, 0, 0x00, 88, 88 ); - TEST_VSETCFGIVL( 150, 24, 0, 0x00, 89, 88 ); - TEST_VSETCFGIVL( 151, 24, 0, 0x00, 87, 87 ); - - #TEST_VSETCFGIVL( 152, 25, 0, 0xf8, 30, 30 ); - #TEST_VSETCFGIVL( 153, 25, 0, 0xf8, 31, 30 ); - #TEST_VSETCFGIVL( 154, 25, 0, 0xf8, 29, 29 ); - - TEST_VSETCFGIVL( 155, 25, 0, 0x00, 80, 80 ); - TEST_VSETCFGIVL( 156, 25, 0, 0x00, 81, 80 ); - TEST_VSETCFGIVL( 157, 25, 0, 0x00, 79, 79 ); - - #TEST_VSETCFGIVL( 158, 26, 0, 0xf8, 30, 30 ); - #TEST_VSETCFGIVL( 159, 26, 0, 0xf8, 31, 30 ); - #TEST_VSETCFGIVL( 160, 26, 0, 0xf8, 29, 29 ); - - TEST_VSETCFGIVL( 161, 26, 0, 0x00, 80, 80 ); - TEST_VSETCFGIVL( 162, 26, 0, 0x00, 81, 80 ); - TEST_VSETCFGIVL( 163, 26, 0, 0x00, 79, 79 ); - - #TEST_VSETCFGIVL( 164, 27, 0, 0xf8, 27, 27 ); - #TEST_VSETCFGIVL( 165, 27, 0, 0xf8, 28, 27 ); - #TEST_VSETCFGIVL( 166, 27, 0, 0xf8, 26, 26 ); - - TEST_VSETCFGIVL( 167, 27, 0, 0x00, 72, 72 ); - TEST_VSETCFGIVL( 168, 27, 0, 0x00, 73, 72 ); - TEST_VSETCFGIVL( 169, 27, 0, 0x00, 71, 71 ); - - #TEST_VSETCFGIVL( 170, 28, 0, 0xf8, 27, 27 ); - #TEST_VSETCFGIVL( 171, 28, 0, 0xf8, 28, 27 ); - #TEST_VSETCFGIVL( 172, 28, 0, 0xf8, 26, 26 ); - - TEST_VSETCFGIVL( 173, 28, 0, 0x00, 72, 72 ); - TEST_VSETCFGIVL( 174, 28, 0, 0x00, 73, 72 ); - TEST_VSETCFGIVL( 175, 28, 0, 0x00, 71, 71 ); - - #TEST_VSETCFGIVL( 176, 29, 0, 0xf8, 27, 27 ); - #TEST_VSETCFGIVL( 177, 29, 0, 0xf8, 28, 27 ); - #TEST_VSETCFGIVL( 178, 29, 0, 0xf8, 26, 26 ); - - TEST_VSETCFGIVL( 179, 29, 0, 0x00, 72, 72 ); - TEST_VSETCFGIVL( 180, 29, 0, 0x00, 73, 72 ); - TEST_VSETCFGIVL( 181, 29, 0, 0x00, 71, 71 ); - - #TEST_VSETCFGIVL( 182, 30, 0, 0xf8, 24, 24 ); - #TEST_VSETCFGIVL( 183, 30, 0, 0xf8, 25, 24 ); - #TEST_VSETCFGIVL( 184, 30, 0, 0xf8, 23, 23 ); - - TEST_VSETCFGIVL( 185, 30, 0, 0x00, 64, 64 ); - TEST_VSETCFGIVL( 186, 30, 0, 0x00, 65, 64 ); - TEST_VSETCFGIVL( 187, 30, 0, 0x00, 63, 63 ); - - #TEST_VSETCFGIVL( 188, 31, 0, 0xf8, 24, 24 ); - #TEST_VSETCFGIVL( 189, 31, 0, 0xf8, 25, 24 ); - #TEST_VSETCFGIVL( 190, 31, 0, 0xf8, 23, 23 ); - - TEST_VSETCFGIVL( 191, 31, 0, 0x00, 64, 64 ); - TEST_VSETCFGIVL( 192, 31, 0, 0x00, 65, 64 ); - TEST_VSETCFGIVL( 193, 31, 0, 0x00, 63, 63 ); - - #TEST_VSETCFGIVL( 194, 32, 0, 0xf8, 24, 24 ); - #TEST_VSETCFGIVL( 195, 32, 0, 0xf8, 25, 24 ); - #TEST_VSETCFGIVL( 196, 32, 0, 0xf8, 23, 23 ); - - TEST_VSETCFGIVL( 197, 32, 0, 0x00, 64, 64 ); - TEST_VSETCFGIVL( 198, 32, 0, 0x00, 65, 64 ); - TEST_VSETCFGIVL( 199, 32, 0, 0x00, 63, 63 ); - - #TEST_VSETCFGIVL( 200, 32, 0, 0xf8, 24, 24 ); - #TEST_VSETCFGIVL( 201, 32, 0, 0xf8, 25, 24 ); - #TEST_VSETCFGIVL( 202, 32, 0, 0xf8, 23, 23 ); - - TEST_VSETCFGIVL( 203, 32, 0, 0x00, 64, 64 ); - TEST_VSETCFGIVL( 204, 32, 0, 0x00, 65, 64 ); - TEST_VSETCFGIVL( 205, 32, 0, 0x00, 63, 63 ); - - #TEST_VSETCFGIVL( 206, 32, 1, 0xf8, 24, 24 ); - #TEST_VSETCFGIVL( 207, 32, 1, 0xf8, 25, 24 ); - #TEST_VSETCFGIVL( 208, 32, 1, 0xf8, 23, 23 ); - - TEST_VSETCFGIVL( 209, 32, 1, 0x00, 64, 64 ); - TEST_VSETCFGIVL( 210, 32, 1, 0x00, 65, 64 ); - TEST_VSETCFGIVL( 211, 32, 1, 0x00, 63, 63 ); - - #TEST_VSETCFGIVL( 212, 32, 2, 0xf8, 21, 21 ); - #TEST_VSETCFGIVL( 213, 32, 2, 0xf8, 22, 21 ); - #TEST_VSETCFGIVL( 214, 32, 2, 0xf8, 20, 20 ); - - TEST_VSETCFGIVL( 215, 32, 2, 0x00, 56, 56 ); - TEST_VSETCFGIVL( 216, 32, 2, 0x00, 57, 56 ); - TEST_VSETCFGIVL( 217, 32, 2, 0x00, 55, 55 ); - - #TEST_VSETCFGIVL( 218, 32, 3, 0xf8, 21, 21 ); - #TEST_VSETCFGIVL( 219, 32, 3, 0xf8, 22, 21 ); - #TEST_VSETCFGIVL( 220, 32, 3, 0xf8, 20, 20 ); - - TEST_VSETCFGIVL( 221, 32, 3, 0x00, 56, 56 ); - TEST_VSETCFGIVL( 222, 32, 3, 0x00, 57, 56 ); - TEST_VSETCFGIVL( 223, 32, 3, 0x00, 55, 55 ); - - #TEST_VSETCFGIVL( 224, 32, 4, 0xf8, 21, 21 ); - #TEST_VSETCFGIVL( 225, 32, 4, 0xf8, 22, 21 ); - #TEST_VSETCFGIVL( 226, 32, 4, 0xf8, 20, 20 ); - - TEST_VSETCFGIVL( 227, 32, 4, 0x00, 56, 56 ); - TEST_VSETCFGIVL( 228, 32, 4, 0x00, 57, 56 ); - TEST_VSETCFGIVL( 229, 32, 4, 0x00, 55, 55 ); - - #TEST_VSETCFGIVL( 230, 32, 5, 0xf8, 21, 21 ); - #TEST_VSETCFGIVL( 231, 32, 5, 0xf8, 22, 21 ); - #TEST_VSETCFGIVL( 232, 32, 5, 0xf8, 20, 20 ); - - TEST_VSETCFGIVL( 233, 32, 5, 0x00, 56, 56 ); - TEST_VSETCFGIVL( 234, 32, 5, 0x00, 57, 56 ); - TEST_VSETCFGIVL( 235, 32, 5, 0x00, 55, 55 ); - - #TEST_VSETCFGIVL( 236, 32, 6, 0xf8, 18, 18 ); - #TEST_VSETCFGIVL( 237, 32, 6, 0xf8, 19, 18 ); - #TEST_VSETCFGIVL( 238, 32, 6, 0xf8, 17, 17 ); - - TEST_VSETCFGIVL( 239, 32, 6, 0x00, 48, 48 ); - TEST_VSETCFGIVL( 240, 32, 6, 0x00, 49, 48 ); - TEST_VSETCFGIVL( 241, 32, 6, 0x00, 47, 47 ); - - #TEST_VSETCFGIVL( 242, 32, 7, 0xf8, 18, 18 ); - #TEST_VSETCFGIVL( 243, 32, 7, 0xf8, 19, 18 ); - #TEST_VSETCFGIVL( 244, 32, 7, 0xf8, 17, 17 ); - - TEST_VSETCFGIVL( 245, 32, 7, 0x00, 48, 48 ); - TEST_VSETCFGIVL( 246, 32, 7, 0x00, 49, 48 ); - TEST_VSETCFGIVL( 247, 32, 7, 0x00, 47, 47 ); - - #TEST_VSETCFGIVL( 248, 32, 8, 0xf8, 18, 18 ); - #TEST_VSETCFGIVL( 249, 32, 8, 0xf8, 19, 18 ); - #TEST_VSETCFGIVL( 250, 32, 8, 0xf8, 17, 17 ); - - TEST_VSETCFGIVL( 251, 32, 8, 0x00, 48, 48 ); - TEST_VSETCFGIVL( 252, 32, 8, 0x00, 49, 48 ); - TEST_VSETCFGIVL( 253, 32, 8, 0x00, 47, 47 ); - - #TEST_VSETCFGIVL( 254, 32, 9, 0xf8, 18, 18 ); - #TEST_VSETCFGIVL( 255, 32, 9, 0xf8, 19, 18 ); - #TEST_VSETCFGIVL( 256, 32, 9, 0xf8, 17, 17 ); - - TEST_VSETCFGIVL( 257, 32, 9, 0x00, 48, 48 ); - TEST_VSETCFGIVL( 258, 32, 9, 0x00, 49, 48 ); - TEST_VSETCFGIVL( 259, 32, 9, 0x00, 47, 47 ); - - #TEST_VSETCFGIVL( 260, 32, 10, 0xf8, 18, 18 ); - #TEST_VSETCFGIVL( 261, 32, 10, 0xf8, 19, 18 ); - #TEST_VSETCFGIVL( 262, 32, 10, 0xf8, 17, 17 ); - - TEST_VSETCFGIVL( 263, 32, 10, 0x00, 48, 48 ); - TEST_VSETCFGIVL( 264, 32, 10, 0x00, 49, 48 ); - TEST_VSETCFGIVL( 265, 32, 10, 0x00, 47, 47 ); - - #TEST_VSETCFGIVL( 266, 32, 11, 0xf8, 18, 18 ); - #TEST_VSETCFGIVL( 267, 32, 11, 0xf8, 19, 18 ); - #TEST_VSETCFGIVL( 268, 32, 11, 0xf8, 17, 17 ); - - TEST_VSETCFGIVL( 269, 32, 11, 0x00, 48, 48 ); - TEST_VSETCFGIVL( 270, 32, 11, 0x00, 49, 48 ); - TEST_VSETCFGIVL( 271, 32, 11, 0x00, 47, 47 ); - - #TEST_VSETCFGIVL( 272, 32, 12, 0xf8, 15, 15 ); - #TEST_VSETCFGIVL( 273, 32, 12, 0xf8, 16, 15 ); - #TEST_VSETCFGIVL( 274, 32, 12, 0xf8, 14, 14 ); - - TEST_VSETCFGIVL( 275, 32, 12, 0x00, 40, 40 ); - TEST_VSETCFGIVL( 276, 32, 12, 0x00, 41, 40 ); - TEST_VSETCFGIVL( 277, 32, 12, 0x00, 39, 39 ); - - #TEST_VSETCFGIVL( 278, 32, 13, 0xf8, 15, 15 ); - #TEST_VSETCFGIVL( 279, 32, 13, 0xf8, 16, 15 ); - #TEST_VSETCFGIVL( 280, 32, 13, 0xf8, 14, 14 ); - - TEST_VSETCFGIVL( 281, 32, 13, 0x00, 40, 40 ); - TEST_VSETCFGIVL( 282, 32, 13, 0x00, 41, 40 ); - TEST_VSETCFGIVL( 283, 32, 13, 0x00, 39, 39 ); - - #TEST_VSETCFGIVL( 284, 32, 14, 0xf8, 15, 15 ); - #TEST_VSETCFGIVL( 285, 32, 14, 0xf8, 16, 15 ); - #TEST_VSETCFGIVL( 286, 32, 14, 0xf8, 14, 14 ); - - TEST_VSETCFGIVL( 287, 32, 14, 0x00, 40, 40 ); - TEST_VSETCFGIVL( 288, 32, 14, 0x00, 41, 40 ); - TEST_VSETCFGIVL( 289, 32, 14, 0x00, 39, 39 ); - - #TEST_VSETCFGIVL( 290, 32, 15, 0xf8, 15, 15 ); - #TEST_VSETCFGIVL( 291, 32, 15, 0xf8, 16, 15 ); - #TEST_VSETCFGIVL( 292, 32, 15, 0xf8, 14, 14 ); - - TEST_VSETCFGIVL( 293, 32, 15, 0x00, 40, 40 ); - TEST_VSETCFGIVL( 294, 32, 15, 0x00, 41, 40 ); - TEST_VSETCFGIVL( 295, 32, 15, 0x00, 39, 39 ); - - #TEST_VSETCFGIVL( 296, 32, 16, 0xf8, 15, 15 ); - #TEST_VSETCFGIVL( 297, 32, 16, 0xf8, 16, 15 ); - #TEST_VSETCFGIVL( 298, 32, 16, 0xf8, 14, 14 ); - - TEST_VSETCFGIVL( 299, 32, 16, 0x00, 40, 40 ); - TEST_VSETCFGIVL( 300, 32, 16, 0x00, 41, 40 ); - TEST_VSETCFGIVL( 301, 32, 16, 0x00, 39, 39 ); - - #TEST_VSETCFGIVL( 302, 32, 17, 0xf8, 15, 15 ); - #TEST_VSETCFGIVL( 303, 32, 17, 0xf8, 16, 15 ); - #TEST_VSETCFGIVL( 304, 32, 17, 0xf8, 14, 14 ); - - TEST_VSETCFGIVL( 305, 32, 17, 0x00, 40, 40 ); - TEST_VSETCFGIVL( 306, 32, 17, 0x00, 41, 40 ); - TEST_VSETCFGIVL( 307, 32, 17, 0x00, 39, 39 ); - - #TEST_VSETCFGIVL( 308, 32, 18, 0xf8, 15, 15 ); - #TEST_VSETCFGIVL( 309, 32, 18, 0xf8, 16, 15 ); - #TEST_VSETCFGIVL( 310, 32, 18, 0xf8, 14, 14 ); - - TEST_VSETCFGIVL( 311, 32, 18, 0x00, 40, 40 ); - TEST_VSETCFGIVL( 312, 32, 18, 0x00, 41, 40 ); - TEST_VSETCFGIVL( 313, 32, 18, 0x00, 39, 39 ); - - #TEST_VSETCFGIVL( 314, 32, 19, 0xf8, 15, 15 ); - #TEST_VSETCFGIVL( 315, 32, 19, 0xf8, 16, 15 ); - #TEST_VSETCFGIVL( 316, 32, 19, 0xf8, 14, 14 ); - - TEST_VSETCFGIVL( 317, 32, 19, 0x00, 40, 40 ); - TEST_VSETCFGIVL( 318, 32, 19, 0x00, 41, 40 ); - TEST_VSETCFGIVL( 319, 32, 19, 0x00, 39, 39 ); - - #TEST_VSETCFGIVL( 320, 32, 20, 0xf8, 15, 15 ); - #TEST_VSETCFGIVL( 321, 32, 20, 0xf8, 16, 15 ); - #TEST_VSETCFGIVL( 322, 32, 20, 0xf8, 14, 14 ); - - TEST_VSETCFGIVL( 323, 32, 20, 0x00, 40, 40 ); - TEST_VSETCFGIVL( 324, 32, 20, 0x00, 41, 40 ); - TEST_VSETCFGIVL( 325, 32, 20, 0x00, 39, 39 ); - - #TEST_VSETCFGIVL( 326, 32, 21, 0xf8, 12, 12 ); - #TEST_VSETCFGIVL( 327, 32, 21, 0xf8, 13, 12 ); - #TEST_VSETCFGIVL( 328, 32, 21, 0xf8, 11, 11 ); - - TEST_VSETCFGIVL( 329, 32, 21, 0x00, 32, 32 ); - TEST_VSETCFGIVL( 330, 32, 21, 0x00, 33, 32 ); - TEST_VSETCFGIVL( 331, 32, 21, 0x00, 31, 31 ); - - #TEST_VSETCFGIVL( 332, 32, 22, 0xf8, 12, 12 ); - #TEST_VSETCFGIVL( 333, 32, 22, 0xf8, 13, 12 ); - #TEST_VSETCFGIVL( 334, 32, 22, 0xf8, 11, 11 ); - - TEST_VSETCFGIVL( 335, 32, 22, 0x00, 32, 32 ); - TEST_VSETCFGIVL( 336, 32, 22, 0x00, 33, 32 ); - TEST_VSETCFGIVL( 337, 32, 22, 0x00, 31, 31 ); - - #TEST_VSETCFGIVL( 338, 32, 23, 0xf8, 12, 12 ); - #TEST_VSETCFGIVL( 339, 32, 23, 0xf8, 13, 12 ); - #TEST_VSETCFGIVL( 340, 32, 23, 0xf8, 11, 11 ); - - TEST_VSETCFGIVL( 341, 32, 23, 0x00, 32, 32 ); - TEST_VSETCFGIVL( 342, 32, 23, 0x00, 33, 32 ); - TEST_VSETCFGIVL( 343, 32, 23, 0x00, 31, 31 ); - - #TEST_VSETCFGIVL( 344, 32, 24, 0xf8, 12, 12 ); - #TEST_VSETCFGIVL( 345, 32, 24, 0xf8, 13, 12 ); - #TEST_VSETCFGIVL( 346, 32, 24, 0xf8, 11, 11 ); - - TEST_VSETCFGIVL( 347, 32, 24, 0x00, 32, 32 ); - TEST_VSETCFGIVL( 348, 32, 24, 0x00, 33, 32 ); - TEST_VSETCFGIVL( 349, 32, 24, 0x00, 31, 31 ); - - #TEST_VSETCFGIVL( 350, 32, 25, 0xf8, 12, 12 ); - #TEST_VSETCFGIVL( 351, 32, 25, 0xf8, 13, 12 ); - #TEST_VSETCFGIVL( 352, 32, 25, 0xf8, 11, 11 ); - - TEST_VSETCFGIVL( 353, 32, 25, 0x00, 32, 32 ); - TEST_VSETCFGIVL( 354, 32, 25, 0x00, 33, 32 ); - TEST_VSETCFGIVL( 355, 32, 25, 0x00, 31, 31 ); - - #TEST_VSETCFGIVL( 356, 32, 26, 0xf8, 12, 12 ); - #TEST_VSETCFGIVL( 357, 32, 26, 0xf8, 13, 12 ); - #TEST_VSETCFGIVL( 358, 32, 26, 0xf8, 11, 11 ); - - TEST_VSETCFGIVL( 359, 32, 26, 0x00, 32, 32 ); - TEST_VSETCFGIVL( 360, 32, 26, 0x00, 33, 32 ); - TEST_VSETCFGIVL( 361, 32, 26, 0x00, 31, 31 ); - - #TEST_VSETCFGIVL( 362, 32, 27, 0xf8, 12, 12 ); - #TEST_VSETCFGIVL( 363, 32, 27, 0xf8, 13, 12 ); - #TEST_VSETCFGIVL( 364, 32, 27, 0xf8, 11, 11 ); - - TEST_VSETCFGIVL( 365, 32, 27, 0x00, 32, 32 ); - TEST_VSETCFGIVL( 366, 32, 27, 0x00, 33, 32 ); - TEST_VSETCFGIVL( 367, 32, 27, 0x00, 31, 31 ); - - #TEST_VSETCFGIVL( 368, 32, 28, 0xf8, 12, 12 ); - #TEST_VSETCFGIVL( 369, 32, 28, 0xf8, 13, 12 ); - #TEST_VSETCFGIVL( 370, 32, 28, 0xf8, 11, 11 ); - - TEST_VSETCFGIVL( 371, 32, 28, 0x00, 32, 32 ); - TEST_VSETCFGIVL( 372, 32, 28, 0x00, 33, 32 ); - TEST_VSETCFGIVL( 373, 32, 28, 0x00, 31, 31 ); - - #TEST_VSETCFGIVL( 374, 32, 29, 0xf8, 12, 12 ); - #TEST_VSETCFGIVL( 375, 32, 29, 0xf8, 13, 12 ); - #TEST_VSETCFGIVL( 376, 32, 29, 0xf8, 11, 11 ); - - TEST_VSETCFGIVL( 377, 32, 29, 0x00, 32, 32 ); - TEST_VSETCFGIVL( 378, 32, 29, 0x00, 33, 32 ); - TEST_VSETCFGIVL( 379, 32, 29, 0x00, 31, 31 ); - - #TEST_VSETCFGIVL( 380, 32, 30, 0xf8, 12, 12 ); - #TEST_VSETCFGIVL( 381, 32, 30, 0xf8, 13, 12 ); - #TEST_VSETCFGIVL( 382, 32, 30, 0xf8, 11, 11 ); - - TEST_VSETCFGIVL( 383, 32, 30, 0x00, 32, 32 ); - TEST_VSETCFGIVL( 384, 32, 30, 0x00, 33, 32 ); - TEST_VSETCFGIVL( 385, 32, 30, 0x00, 31, 31 ); - - #TEST_VSETCFGIVL( 386, 32, 31, 0xf8, 12, 12 ); - #TEST_VSETCFGIVL( 387, 32, 31, 0xf8, 13, 12 ); - #TEST_VSETCFGIVL( 388, 32, 31, 0xf8, 11, 11 ); - - TEST_VSETCFGIVL( 389, 32, 31, 0x00, 32, 32 ); - TEST_VSETCFGIVL( 390, 32, 31, 0x00, 33, 32 ); - TEST_VSETCFGIVL( 391, 32, 31, 0x00, 31, 31 ); - - #TEST_VSETCFGIVL( 392, 32, 32, 0xf8, 12, 12 ); - #TEST_VSETCFGIVL( 393, 32, 32, 0xf8, 13, 12 ); - #TEST_VSETCFGIVL( 394, 32, 32, 0xf8, 11, 11 ); - - TEST_VSETCFGIVL( 395, 32, 32, 0x00, 32, 32 ); - TEST_VSETCFGIVL( 396, 32, 32, 0x00, 33, 32 ); - TEST_VSETCFGIVL( 397, 32, 32, 0x00, 31, 31 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64uv/vsetvl.S b/isa/rv64uv/vsetvl.S deleted file mode 100644 index e78020f..0000000 --- a/isa/rv64uv/vsetvl.S +++ /dev/null @@ -1,561 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# vsetvl.S -#----------------------------------------------------------------------------- -# -# Test vsetvl instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - #TEST_VSETVL( 2, 0, 0, 0xf8, 768, 768 ); - #TEST_VSETVL( 3, 0, 0, 0xf8, 769, 768 ); - #TEST_VSETVL( 4, 0, 0, 0xf8, 767, 767 ); - - TEST_VSETVL( 5, 0, 0, 0x00, 2048, 2048 ); - TEST_VSETVL( 6, 0, 0, 0x00, 2049, 2048 ); - TEST_VSETVL( 7, 0, 0, 0x00, 2047, 2047 ); - - #TEST_VSETVL( 8, 1, 0, 0xf8, 768, 768 ); - #TEST_VSETVL( 9, 1, 0, 0xf8, 769, 768 ); - #TEST_VSETVL( 10, 1, 0, 0xf8, 767, 767 ); - - TEST_VSETVL( 11, 1, 0, 0x00, 2048, 2048 ); - TEST_VSETVL( 12, 1, 0, 0x00, 2049, 2048 ); - TEST_VSETVL( 13, 1, 0, 0x00, 2047, 2047 ); - - #TEST_VSETVL( 14, 2, 0, 0xf8, 768, 768 ); - #TEST_VSETVL( 15, 2, 0, 0xf8, 769, 768 ); - #TEST_VSETVL( 16, 2, 0, 0xf8, 767, 767 ); - - TEST_VSETVL( 17, 2, 0, 0x00, 2048, 2048 ); - TEST_VSETVL( 18, 2, 0, 0x00, 2049, 2048 ); - TEST_VSETVL( 19, 2, 0, 0x00, 2047, 2047 ); - - #TEST_VSETVL( 20, 3, 0, 0xf8, 384, 384 ); - #TEST_VSETVL( 21, 3, 0, 0xf8, 385, 384 ); - #TEST_VSETVL( 22, 3, 0, 0xf8, 383, 383 ); - - TEST_VSETVL( 23, 3, 0, 0x00, 1024, 1024 ); - TEST_VSETVL( 24, 3, 0, 0x00, 1025, 1024 ); - TEST_VSETVL( 25, 3, 0, 0x00, 1023, 1023 ); - - #TEST_VSETVL( 26, 4, 0, 0xf8, 255, 255 ); - #TEST_VSETVL( 27, 4, 0, 0xf8, 256, 255 ); - #TEST_VSETVL( 28, 4, 0, 0xf8, 254, 254 ); - - TEST_VSETVL( 29, 4, 0, 0x00, 680, 680 ); - TEST_VSETVL( 30, 4, 0, 0x00, 681, 680 ); - TEST_VSETVL( 31, 4, 0, 0x00, 679, 679 ); - - #TEST_VSETVL( 32, 5, 0, 0xf8, 192, 192 ); - #TEST_VSETVL( 33, 5, 0, 0xf8, 193, 192 ); - #TEST_VSETVL( 34, 5, 0, 0xf8, 191, 191 ); - - TEST_VSETVL( 35, 5, 0, 0x00, 512, 512 ); - TEST_VSETVL( 36, 5, 0, 0x00, 513, 512 ); - TEST_VSETVL( 37, 5, 0, 0x00, 511, 511 ); - - #TEST_VSETVL( 38, 6, 0, 0xf8, 153, 153 ); - #TEST_VSETVL( 39, 6, 0, 0xf8, 154, 153 ); - #TEST_VSETVL( 40, 6, 0, 0xf8, 152, 152 ); - - TEST_VSETVL( 41, 6, 0, 0x00, 408, 408 ); - TEST_VSETVL( 42, 6, 0, 0x00, 409, 408 ); - TEST_VSETVL( 43, 6, 0, 0x00, 407, 407 ); - - #TEST_VSETVL( 44, 7, 0, 0xf8, 126, 126 ); - #TEST_VSETVL( 45, 7, 0, 0xf8, 127, 126 ); - #TEST_VSETVL( 46, 7, 0, 0xf8, 125, 125 ); - - TEST_VSETVL( 47, 7, 0, 0x00, 336, 336 ); - TEST_VSETVL( 48, 7, 0, 0x00, 337, 336 ); - TEST_VSETVL( 49, 7, 0, 0x00, 335, 335 ); - - #TEST_VSETVL( 50, 8, 0, 0xf8, 108, 108 ); - #TEST_VSETVL( 51, 8, 0, 0xf8, 109, 108 ); - #TEST_VSETVL( 52, 8, 0, 0xf8, 107, 107 ); - - TEST_VSETVL( 53, 8, 0, 0x00, 288, 288 ); - TEST_VSETVL( 54, 8, 0, 0x00, 289, 288 ); - TEST_VSETVL( 55, 8, 0, 0x00, 287, 287 ); - - #TEST_VSETVL( 56, 9, 0, 0xf8, 96, 96 ); - #TEST_VSETVL( 57, 9, 0, 0xf8, 97, 96 ); - #TEST_VSETVL( 58, 9, 0, 0xf8, 95, 95 ); - - TEST_VSETVL( 59, 9, 0, 0x00, 256, 256 ); - TEST_VSETVL( 60, 9, 0, 0x00, 257, 256 ); - TEST_VSETVL( 61, 9, 0, 0x00, 255, 255 ); - - #TEST_VSETVL( 62, 10, 0, 0xf8, 84, 84 ); - #TEST_VSETVL( 63, 10, 0, 0xf8, 85, 84 ); - #TEST_VSETVL( 64, 10, 0, 0xf8, 83, 83 ); - - TEST_VSETVL( 65, 10, 0, 0x00, 224, 224 ); - TEST_VSETVL( 66, 10, 0, 0x00, 225, 224 ); - TEST_VSETVL( 67, 10, 0, 0x00, 223, 223 ); - - #TEST_VSETVL( 68, 11, 0, 0xf8, 75, 75 ); - #TEST_VSETVL( 69, 11, 0, 0xf8, 76, 75 ); - #TEST_VSETVL( 70, 11, 0, 0xf8, 74, 74 ); - - TEST_VSETVL( 71, 11, 0, 0x00, 200, 200 ); - TEST_VSETVL( 72, 11, 0, 0x00, 201, 200 ); - TEST_VSETVL( 73, 11, 0, 0x00, 199, 199 ); - - #TEST_VSETVL( 74, 12, 0, 0xf8, 69, 69 ); - #TEST_VSETVL( 75, 12, 0, 0xf8, 70, 69 ); - #TEST_VSETVL( 76, 12, 0, 0xf8, 68, 68 ); - - TEST_VSETVL( 77, 12, 0, 0x00, 184, 184 ); - TEST_VSETVL( 78, 12, 0, 0x00, 185, 184 ); - TEST_VSETVL( 79, 12, 0, 0x00, 183, 183 ); - - #TEST_VSETVL( 80, 13, 0, 0xf8, 63, 63 ); - #TEST_VSETVL( 81, 13, 0, 0xf8, 64, 63 ); - #TEST_VSETVL( 82, 13, 0, 0xf8, 62, 62 ); - - TEST_VSETVL( 83, 13, 0, 0x00, 168, 168 ); - TEST_VSETVL( 84, 13, 0, 0x00, 169, 168 ); - TEST_VSETVL( 85, 13, 0, 0x00, 167, 167 ); - - #TEST_VSETVL( 86, 14, 0, 0xf8, 57, 57 ); - #TEST_VSETVL( 87, 14, 0, 0xf8, 58, 57 ); - #TEST_VSETVL( 88, 14, 0, 0xf8, 56, 56 ); - - TEST_VSETVL( 89, 14, 0, 0x00, 152, 152 ); - TEST_VSETVL( 90, 14, 0, 0x00, 153, 152 ); - TEST_VSETVL( 91, 14, 0, 0x00, 151, 151 ); - - #TEST_VSETVL( 92, 15, 0, 0xf8, 54, 54 ); - #TEST_VSETVL( 93, 15, 0, 0xf8, 55, 54 ); - #TEST_VSETVL( 94, 15, 0, 0xf8, 53, 53 ); - - TEST_VSETVL( 95, 15, 0, 0x00, 144, 144 ); - TEST_VSETVL( 96, 15, 0, 0x00, 145, 144 ); - TEST_VSETVL( 97, 15, 0, 0x00, 143, 143 ); - - #TEST_VSETVL( 98, 16, 0, 0xf8, 51, 51 ); - #TEST_VSETVL( 99, 16, 0, 0xf8, 52, 51 ); - #TEST_VSETVL( 100, 16, 0, 0xf8, 50, 50 ); - - TEST_VSETVL( 101, 16, 0, 0x00, 136, 136 ); - TEST_VSETVL( 102, 16, 0, 0x00, 137, 136 ); - TEST_VSETVL( 103, 16, 0, 0x00, 135, 135 ); - - #TEST_VSETVL( 104, 17, 0, 0xf8, 48, 48 ); - #TEST_VSETVL( 105, 17, 0, 0xf8, 49, 48 ); - #TEST_VSETVL( 106, 17, 0, 0xf8, 47, 47 ); - - TEST_VSETVL( 107, 17, 0, 0x00, 128, 128 ); - TEST_VSETVL( 108, 17, 0, 0x00, 129, 128 ); - TEST_VSETVL( 109, 17, 0, 0x00, 127, 127 ); - - #TEST_VSETVL( 110, 18, 0, 0xf8, 45, 45 ); - #TEST_VSETVL( 111, 18, 0, 0xf8, 46, 45 ); - #TEST_VSETVL( 112, 18, 0, 0xf8, 44, 44 ); - - TEST_VSETVL( 113, 18, 0, 0x00, 120, 120 ); - TEST_VSETVL( 114, 18, 0, 0x00, 121, 120 ); - TEST_VSETVL( 115, 18, 0, 0x00, 119, 119 ); - - #TEST_VSETVL( 116, 19, 0, 0xf8, 42, 42 ); - #TEST_VSETVL( 117, 19, 0, 0xf8, 43, 42 ); - #TEST_VSETVL( 118, 19, 0, 0xf8, 41, 41 ); - - TEST_VSETVL( 119, 19, 0, 0x00, 112, 112 ); - TEST_VSETVL( 120, 19, 0, 0x00, 113, 112 ); - TEST_VSETVL( 121, 19, 0, 0x00, 111, 111 ); - - #TEST_VSETVL( 122, 20, 0, 0xf8, 39, 39 ); - #TEST_VSETVL( 123, 20, 0, 0xf8, 40, 39 ); - #TEST_VSETVL( 124, 20, 0, 0xf8, 38, 38 ); - - TEST_VSETVL( 125, 20, 0, 0x00, 104, 104 ); - TEST_VSETVL( 126, 20, 0, 0x00, 105, 104 ); - TEST_VSETVL( 127, 20, 0, 0x00, 103, 103 ); - - #TEST_VSETVL( 128, 21, 0, 0xf8, 36, 36 ); - #TEST_VSETVL( 129, 21, 0, 0xf8, 37, 36 ); - #TEST_VSETVL( 130, 21, 0, 0xf8, 35, 35 ); - - TEST_VSETVL( 131, 21, 0, 0x00, 96, 96 ); - TEST_VSETVL( 132, 21, 0, 0x00, 97, 96 ); - TEST_VSETVL( 133, 21, 0, 0x00, 95, 95 ); - - #TEST_VSETVL( 134, 22, 0, 0xf8, 36, 36 ); - #TEST_VSETVL( 135, 22, 0, 0xf8, 37, 36 ); - #TEST_VSETVL( 136, 22, 0, 0xf8, 35, 35 ); - - TEST_VSETVL( 137, 22, 0, 0x00, 96, 96 ); - TEST_VSETVL( 138, 22, 0, 0x00, 97, 96 ); - TEST_VSETVL( 139, 22, 0, 0x00, 95, 95 ); - - #TEST_VSETVL( 140, 23, 0, 0xf8, 33, 33 ); - #TEST_VSETVL( 141, 23, 0, 0xf8, 34, 33 ); - #TEST_VSETVL( 142, 23, 0, 0xf8, 32, 32 ); - - TEST_VSETVL( 143, 23, 0, 0x00, 88, 88 ); - TEST_VSETVL( 144, 23, 0, 0x00, 89, 88 ); - TEST_VSETVL( 145, 23, 0, 0x00, 87, 87 ); - - #TEST_VSETVL( 146, 24, 0, 0xf8, 33, 33 ); - #TEST_VSETVL( 147, 24, 0, 0xf8, 34, 33 ); - #TEST_VSETVL( 148, 24, 0, 0xf8, 32, 32 ); - - TEST_VSETVL( 149, 24, 0, 0x00, 88, 88 ); - TEST_VSETVL( 150, 24, 0, 0x00, 89, 88 ); - TEST_VSETVL( 151, 24, 0, 0x00, 87, 87 ); - - #TEST_VSETVL( 152, 25, 0, 0xf8, 30, 30 ); - #TEST_VSETVL( 153, 25, 0, 0xf8, 31, 30 ); - #TEST_VSETVL( 154, 25, 0, 0xf8, 29, 29 ); - - TEST_VSETVL( 155, 25, 0, 0x00, 80, 80 ); - TEST_VSETVL( 156, 25, 0, 0x00, 81, 80 ); - TEST_VSETVL( 157, 25, 0, 0x00, 79, 79 ); - - #TEST_VSETVL( 158, 26, 0, 0xf8, 30, 30 ); - #TEST_VSETVL( 159, 26, 0, 0xf8, 31, 30 ); - #TEST_VSETVL( 160, 26, 0, 0xf8, 29, 29 ); - - TEST_VSETVL( 161, 26, 0, 0x00, 80, 80 ); - TEST_VSETVL( 162, 26, 0, 0x00, 81, 80 ); - TEST_VSETVL( 163, 26, 0, 0x00, 79, 79 ); - - #TEST_VSETVL( 164, 27, 0, 0xf8, 27, 27 ); - #TEST_VSETVL( 165, 27, 0, 0xf8, 28, 27 ); - #TEST_VSETVL( 166, 27, 0, 0xf8, 26, 26 ); - - TEST_VSETVL( 167, 27, 0, 0x00, 72, 72 ); - TEST_VSETVL( 168, 27, 0, 0x00, 73, 72 ); - TEST_VSETVL( 169, 27, 0, 0x00, 71, 71 ); - - #TEST_VSETVL( 170, 28, 0, 0xf8, 27, 27 ); - #TEST_VSETVL( 171, 28, 0, 0xf8, 28, 27 ); - #TEST_VSETVL( 172, 28, 0, 0xf8, 26, 26 ); - - TEST_VSETVL( 173, 28, 0, 0x00, 72, 72 ); - TEST_VSETVL( 174, 28, 0, 0x00, 73, 72 ); - TEST_VSETVL( 175, 28, 0, 0x00, 71, 71 ); - - #TEST_VSETVL( 176, 29, 0, 0xf8, 27, 27 ); - #TEST_VSETVL( 177, 29, 0, 0xf8, 28, 27 ); - #TEST_VSETVL( 178, 29, 0, 0xf8, 26, 26 ); - - TEST_VSETVL( 179, 29, 0, 0x00, 72, 72 ); - TEST_VSETVL( 180, 29, 0, 0x00, 73, 72 ); - TEST_VSETVL( 181, 29, 0, 0x00, 71, 71 ); - - #TEST_VSETVL( 182, 30, 0, 0xf8, 24, 24 ); - #TEST_VSETVL( 183, 30, 0, 0xf8, 25, 24 ); - #TEST_VSETVL( 184, 30, 0, 0xf8, 23, 23 ); - - TEST_VSETVL( 185, 30, 0, 0x00, 64, 64 ); - TEST_VSETVL( 186, 30, 0, 0x00, 65, 64 ); - TEST_VSETVL( 187, 30, 0, 0x00, 63, 63 ); - - #TEST_VSETVL( 188, 31, 0, 0xf8, 24, 24 ); - #TEST_VSETVL( 189, 31, 0, 0xf8, 25, 24 ); - #TEST_VSETVL( 190, 31, 0, 0xf8, 23, 23 ); - - TEST_VSETVL( 191, 31, 0, 0x00, 64, 64 ); - TEST_VSETVL( 192, 31, 0, 0x00, 65, 64 ); - TEST_VSETVL( 193, 31, 0, 0x00, 63, 63 ); - - #TEST_VSETVL( 194, 32, 0, 0xf8, 24, 24 ); - #TEST_VSETVL( 195, 32, 0, 0xf8, 25, 24 ); - #TEST_VSETVL( 196, 32, 0, 0xf8, 23, 23 ); - - TEST_VSETVL( 197, 32, 0, 0x00, 64, 64 ); - TEST_VSETVL( 198, 32, 0, 0x00, 65, 64 ); - TEST_VSETVL( 199, 32, 0, 0x00, 63, 63 ); - - #TEST_VSETVL( 200, 32, 0, 0xf8, 24, 24 ); - #TEST_VSETVL( 201, 32, 0, 0xf8, 25, 24 ); - #TEST_VSETVL( 202, 32, 0, 0xf8, 23, 23 ); - - TEST_VSETVL( 203, 32, 0, 0x00, 64, 64 ); - TEST_VSETVL( 204, 32, 0, 0x00, 65, 64 ); - TEST_VSETVL( 205, 32, 0, 0x00, 63, 63 ); - - #TEST_VSETVL( 206, 32, 1, 0xf8, 24, 24 ); - #TEST_VSETVL( 207, 32, 1, 0xf8, 25, 24 ); - #TEST_VSETVL( 208, 32, 1, 0xf8, 23, 23 ); - - TEST_VSETVL( 209, 32, 1, 0x00, 64, 64 ); - TEST_VSETVL( 210, 32, 1, 0x00, 65, 64 ); - TEST_VSETVL( 211, 32, 1, 0x00, 63, 63 ); - - #TEST_VSETVL( 212, 32, 2, 0xf8, 21, 21 ); - #TEST_VSETVL( 213, 32, 2, 0xf8, 22, 21 ); - #TEST_VSETVL( 214, 32, 2, 0xf8, 20, 20 ); - - TEST_VSETVL( 215, 32, 2, 0x00, 56, 56 ); - TEST_VSETVL( 216, 32, 2, 0x00, 57, 56 ); - TEST_VSETVL( 217, 32, 2, 0x00, 55, 55 ); - - #TEST_VSETVL( 218, 32, 3, 0xf8, 21, 21 ); - #TEST_VSETVL( 219, 32, 3, 0xf8, 22, 21 ); - #TEST_VSETVL( 220, 32, 3, 0xf8, 20, 20 ); - - TEST_VSETVL( 221, 32, 3, 0x00, 56, 56 ); - TEST_VSETVL( 222, 32, 3, 0x00, 57, 56 ); - TEST_VSETVL( 223, 32, 3, 0x00, 55, 55 ); - - #TEST_VSETVL( 224, 32, 4, 0xf8, 21, 21 ); - #TEST_VSETVL( 225, 32, 4, 0xf8, 22, 21 ); - #TEST_VSETVL( 226, 32, 4, 0xf8, 20, 20 ); - - TEST_VSETVL( 227, 32, 4, 0x00, 56, 56 ); - TEST_VSETVL( 228, 32, 4, 0x00, 57, 56 ); - TEST_VSETVL( 229, 32, 4, 0x00, 55, 55 ); - - #TEST_VSETVL( 230, 32, 5, 0xf8, 21, 21 ); - #TEST_VSETVL( 231, 32, 5, 0xf8, 22, 21 ); - #TEST_VSETVL( 232, 32, 5, 0xf8, 20, 20 ); - - TEST_VSETVL( 233, 32, 5, 0x00, 56, 56 ); - TEST_VSETVL( 234, 32, 5, 0x00, 57, 56 ); - TEST_VSETVL( 235, 32, 5, 0x00, 55, 55 ); - - #TEST_VSETVL( 236, 32, 6, 0xf8, 18, 18 ); - #TEST_VSETVL( 237, 32, 6, 0xf8, 19, 18 ); - #TEST_VSETVL( 238, 32, 6, 0xf8, 17, 17 ); - - TEST_VSETVL( 239, 32, 6, 0x00, 48, 48 ); - TEST_VSETVL( 240, 32, 6, 0x00, 49, 48 ); - TEST_VSETVL( 241, 32, 6, 0x00, 47, 47 ); - - #TEST_VSETVL( 242, 32, 7, 0xf8, 18, 18 ); - #TEST_VSETVL( 243, 32, 7, 0xf8, 19, 18 ); - #TEST_VSETVL( 244, 32, 7, 0xf8, 17, 17 ); - - TEST_VSETVL( 245, 32, 7, 0x00, 48, 48 ); - TEST_VSETVL( 246, 32, 7, 0x00, 49, 48 ); - TEST_VSETVL( 247, 32, 7, 0x00, 47, 47 ); - - #TEST_VSETVL( 248, 32, 8, 0xf8, 18, 18 ); - #TEST_VSETVL( 249, 32, 8, 0xf8, 19, 18 ); - #TEST_VSETVL( 250, 32, 8, 0xf8, 17, 17 ); - - TEST_VSETVL( 251, 32, 8, 0x00, 48, 48 ); - TEST_VSETVL( 252, 32, 8, 0x00, 49, 48 ); - TEST_VSETVL( 253, 32, 8, 0x00, 47, 47 ); - - #TEST_VSETVL( 254, 32, 9, 0xf8, 18, 18 ); - #TEST_VSETVL( 255, 32, 9, 0xf8, 19, 18 ); - #TEST_VSETVL( 256, 32, 9, 0xf8, 17, 17 ); - - TEST_VSETVL( 257, 32, 9, 0x00, 48, 48 ); - TEST_VSETVL( 258, 32, 9, 0x00, 49, 48 ); - TEST_VSETVL( 259, 32, 9, 0x00, 47, 47 ); - - #TEST_VSETVL( 260, 32, 10, 0xf8, 18, 18 ); - #TEST_VSETVL( 261, 32, 10, 0xf8, 19, 18 ); - #TEST_VSETVL( 262, 32, 10, 0xf8, 17, 17 ); - - TEST_VSETVL( 263, 32, 10, 0x00, 48, 48 ); - TEST_VSETVL( 264, 32, 10, 0x00, 49, 48 ); - TEST_VSETVL( 265, 32, 10, 0x00, 47, 47 ); - - #TEST_VSETVL( 266, 32, 11, 0xf8, 18, 18 ); - #TEST_VSETVL( 267, 32, 11, 0xf8, 19, 18 ); - #TEST_VSETVL( 268, 32, 11, 0xf8, 17, 17 ); - - TEST_VSETVL( 269, 32, 11, 0x00, 48, 48 ); - TEST_VSETVL( 270, 32, 11, 0x00, 49, 48 ); - TEST_VSETVL( 271, 32, 11, 0x00, 47, 47 ); - - #TEST_VSETVL( 272, 32, 12, 0xf8, 15, 15 ); - #TEST_VSETVL( 273, 32, 12, 0xf8, 16, 15 ); - #TEST_VSETVL( 274, 32, 12, 0xf8, 14, 14 ); - - TEST_VSETVL( 275, 32, 12, 0x00, 40, 40 ); - TEST_VSETVL( 276, 32, 12, 0x00, 41, 40 ); - TEST_VSETVL( 277, 32, 12, 0x00, 39, 39 ); - - #TEST_VSETVL( 278, 32, 13, 0xf8, 15, 15 ); - #TEST_VSETVL( 279, 32, 13, 0xf8, 16, 15 ); - #TEST_VSETVL( 280, 32, 13, 0xf8, 14, 14 ); - - TEST_VSETVL( 281, 32, 13, 0x00, 40, 40 ); - TEST_VSETVL( 282, 32, 13, 0x00, 41, 40 ); - TEST_VSETVL( 283, 32, 13, 0x00, 39, 39 ); - - #TEST_VSETVL( 284, 32, 14, 0xf8, 15, 15 ); - #TEST_VSETVL( 285, 32, 14, 0xf8, 16, 15 ); - #TEST_VSETVL( 286, 32, 14, 0xf8, 14, 14 ); - - TEST_VSETVL( 287, 32, 14, 0x00, 40, 40 ); - TEST_VSETVL( 288, 32, 14, 0x00, 41, 40 ); - TEST_VSETVL( 289, 32, 14, 0x00, 39, 39 ); - - #TEST_VSETVL( 290, 32, 15, 0xf8, 15, 15 ); - #TEST_VSETVL( 291, 32, 15, 0xf8, 16, 15 ); - #TEST_VSETVL( 292, 32, 15, 0xf8, 14, 14 ); - - TEST_VSETVL( 293, 32, 15, 0x00, 40, 40 ); - TEST_VSETVL( 294, 32, 15, 0x00, 41, 40 ); - TEST_VSETVL( 295, 32, 15, 0x00, 39, 39 ); - - #TEST_VSETVL( 296, 32, 16, 0xf8, 15, 15 ); - #TEST_VSETVL( 297, 32, 16, 0xf8, 16, 15 ); - #TEST_VSETVL( 298, 32, 16, 0xf8, 14, 14 ); - - TEST_VSETVL( 299, 32, 16, 0x00, 40, 40 ); - TEST_VSETVL( 300, 32, 16, 0x00, 41, 40 ); - TEST_VSETVL( 301, 32, 16, 0x00, 39, 39 ); - - #TEST_VSETVL( 302, 32, 17, 0xf8, 15, 15 ); - #TEST_VSETVL( 303, 32, 17, 0xf8, 16, 15 ); - #TEST_VSETVL( 304, 32, 17, 0xf8, 14, 14 ); - - TEST_VSETVL( 305, 32, 17, 0x00, 40, 40 ); - TEST_VSETVL( 306, 32, 17, 0x00, 41, 40 ); - TEST_VSETVL( 307, 32, 17, 0x00, 39, 39 ); - - #TEST_VSETVL( 308, 32, 18, 0xf8, 15, 15 ); - #TEST_VSETVL( 309, 32, 18, 0xf8, 16, 15 ); - #TEST_VSETVL( 310, 32, 18, 0xf8, 14, 14 ); - - TEST_VSETVL( 311, 32, 18, 0x00, 40, 40 ); - TEST_VSETVL( 312, 32, 18, 0x00, 41, 40 ); - TEST_VSETVL( 313, 32, 18, 0x00, 39, 39 ); - - #TEST_VSETVL( 314, 32, 19, 0xf8, 15, 15 ); - #TEST_VSETVL( 315, 32, 19, 0xf8, 16, 15 ); - #TEST_VSETVL( 316, 32, 19, 0xf8, 14, 14 ); - - TEST_VSETVL( 317, 32, 19, 0x00, 40, 40 ); - TEST_VSETVL( 318, 32, 19, 0x00, 41, 40 ); - TEST_VSETVL( 319, 32, 19, 0x00, 39, 39 ); - - #TEST_VSETVL( 320, 32, 20, 0xf8, 15, 15 ); - #TEST_VSETVL( 321, 32, 20, 0xf8, 16, 15 ); - #TEST_VSETVL( 322, 32, 20, 0xf8, 14, 14 ); - - TEST_VSETVL( 323, 32, 20, 0x00, 40, 40 ); - TEST_VSETVL( 324, 32, 20, 0x00, 41, 40 ); - TEST_VSETVL( 325, 32, 20, 0x00, 39, 39 ); - - #TEST_VSETVL( 326, 32, 21, 0xf8, 12, 12 ); - #TEST_VSETVL( 327, 32, 21, 0xf8, 13, 12 ); - #TEST_VSETVL( 328, 32, 21, 0xf8, 11, 11 ); - - TEST_VSETVL( 329, 32, 21, 0x00, 32, 32 ); - TEST_VSETVL( 330, 32, 21, 0x00, 33, 32 ); - TEST_VSETVL( 331, 32, 21, 0x00, 31, 31 ); - - #TEST_VSETVL( 332, 32, 22, 0xf8, 12, 12 ); - #TEST_VSETVL( 333, 32, 22, 0xf8, 13, 12 ); - #TEST_VSETVL( 334, 32, 22, 0xf8, 11, 11 ); - - TEST_VSETVL( 335, 32, 22, 0x00, 32, 32 ); - TEST_VSETVL( 336, 32, 22, 0x00, 33, 32 ); - TEST_VSETVL( 337, 32, 22, 0x00, 31, 31 ); - - #TEST_VSETVL( 338, 32, 23, 0xf8, 12, 12 ); - #TEST_VSETVL( 339, 32, 23, 0xf8, 13, 12 ); - #TEST_VSETVL( 340, 32, 23, 0xf8, 11, 11 ); - - TEST_VSETVL( 341, 32, 23, 0x00, 32, 32 ); - TEST_VSETVL( 342, 32, 23, 0x00, 33, 32 ); - TEST_VSETVL( 343, 32, 23, 0x00, 31, 31 ); - - #TEST_VSETVL( 344, 32, 24, 0xf8, 12, 12 ); - #TEST_VSETVL( 345, 32, 24, 0xf8, 13, 12 ); - #TEST_VSETVL( 346, 32, 24, 0xf8, 11, 11 ); - - TEST_VSETVL( 347, 32, 24, 0x00, 32, 32 ); - TEST_VSETVL( 348, 32, 24, 0x00, 33, 32 ); - TEST_VSETVL( 349, 32, 24, 0x00, 31, 31 ); - - #TEST_VSETVL( 350, 32, 25, 0xf8, 12, 12 ); - #TEST_VSETVL( 351, 32, 25, 0xf8, 13, 12 ); - #TEST_VSETVL( 352, 32, 25, 0xf8, 11, 11 ); - - TEST_VSETVL( 353, 32, 25, 0x00, 32, 32 ); - TEST_VSETVL( 354, 32, 25, 0x00, 33, 32 ); - TEST_VSETVL( 355, 32, 25, 0x00, 31, 31 ); - - #TEST_VSETVL( 356, 32, 26, 0xf8, 12, 12 ); - #TEST_VSETVL( 357, 32, 26, 0xf8, 13, 12 ); - #TEST_VSETVL( 358, 32, 26, 0xf8, 11, 11 ); - - TEST_VSETVL( 359, 32, 26, 0x00, 32, 32 ); - TEST_VSETVL( 360, 32, 26, 0x00, 33, 32 ); - TEST_VSETVL( 361, 32, 26, 0x00, 31, 31 ); - - #TEST_VSETVL( 362, 32, 27, 0xf8, 12, 12 ); - #TEST_VSETVL( 363, 32, 27, 0xf8, 13, 12 ); - #TEST_VSETVL( 364, 32, 27, 0xf8, 11, 11 ); - - TEST_VSETVL( 365, 32, 27, 0x00, 32, 32 ); - TEST_VSETVL( 366, 32, 27, 0x00, 33, 32 ); - TEST_VSETVL( 367, 32, 27, 0x00, 31, 31 ); - - #TEST_VSETVL( 368, 32, 28, 0xf8, 12, 12 ); - #TEST_VSETVL( 369, 32, 28, 0xf8, 13, 12 ); - #TEST_VSETVL( 370, 32, 28, 0xf8, 11, 11 ); - - TEST_VSETVL( 371, 32, 28, 0x00, 32, 32 ); - TEST_VSETVL( 372, 32, 28, 0x00, 33, 32 ); - TEST_VSETVL( 373, 32, 28, 0x00, 31, 31 ); - - #TEST_VSETVL( 374, 32, 29, 0xf8, 12, 12 ); - #TEST_VSETVL( 375, 32, 29, 0xf8, 13, 12 ); - #TEST_VSETVL( 376, 32, 29, 0xf8, 11, 11 ); - - TEST_VSETVL( 377, 32, 29, 0x00, 32, 32 ); - TEST_VSETVL( 378, 32, 29, 0x00, 33, 32 ); - TEST_VSETVL( 379, 32, 29, 0x00, 31, 31 ); - - #TEST_VSETVL( 380, 32, 30, 0xf8, 12, 12 ); - #TEST_VSETVL( 381, 32, 30, 0xf8, 13, 12 ); - #TEST_VSETVL( 382, 32, 30, 0xf8, 11, 11 ); - - TEST_VSETVL( 383, 32, 30, 0x00, 32, 32 ); - TEST_VSETVL( 384, 32, 30, 0x00, 33, 32 ); - TEST_VSETVL( 385, 32, 30, 0x00, 31, 31 ); - - #TEST_VSETVL( 386, 32, 31, 0xf8, 12, 12 ); - #TEST_VSETVL( 387, 32, 31, 0xf8, 13, 12 ); - #TEST_VSETVL( 388, 32, 31, 0xf8, 11, 11 ); - - TEST_VSETVL( 389, 32, 31, 0x00, 32, 32 ); - TEST_VSETVL( 390, 32, 31, 0x00, 33, 32 ); - TEST_VSETVL( 391, 32, 31, 0x00, 31, 31 ); - - #TEST_VSETVL( 392, 32, 32, 0xf8, 12, 12 ); - #TEST_VSETVL( 393, 32, 32, 0xf8, 13, 12 ); - #TEST_VSETVL( 394, 32, 32, 0xf8, 11, 11 ); - - TEST_VSETVL( 395, 32, 32, 0x00, 32, 32 ); - TEST_VSETVL( 396, 32, 32, 0x00, 33, 32 ); - TEST_VSETVL( 397, 32, 32, 0x00, 31, 31 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64uv/vvadd_branch.S b/isa/rv64uv/vvadd_branch.S deleted file mode 100644 index e95dc82..0000000 --- a/isa/rv64uv/vvadd_branch.S +++ /dev/null @@ -1,144 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# vvadd_branch.S -#----------------------------------------------------------------------------- -# -# Test vvadd branch. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - la a3,src1 - la a4,src2 - vld vx2,a3 - vld vx3,a4 - lui a0,%hi(vtcode1) - vf %lo(vtcode1)(a0) - la a5,dest - vsd vx2,a5 - fence - - ld a1,0(a5) - li a2,8 - li TESTNUM,2 - bne a1,a2,fail - ld a1,8(a5) - li a2, 6 - li TESTNUM,3 - bne a1,a2,fail - ld a1,16(a5) - li a2, 4 - li TESTNUM,4 - bne a1,a2,fail - li a2, 2 - ld a1,24(a5) - li TESTNUM,5 - bne a1,a2,fail - - la a3,src1 - vld vx4,a3 - li a4, 3 - vmsv vx5,a4 - lui a0,%hi(vtcode2) - vf %lo(vtcode2)(a0) - la a5,dest - vsd vx4,a5 - fence - - ld a1,0(a5) - li a2,1 - li TESTNUM,6 - bne a1,a2,fail - ld a1,8(a5) - li a2,2 - li TESTNUM,7 - bne a1,a2,fail - ld a1,16(a5) - li a2,0 - li TESTNUM,8 - bne a1,a2,fail - ld a1,24(a5) - li a2,0 - li TESTNUM,9 - bne a1,a2,fail - - la a3,src2 - vld vx5,a3 - lui a0,%hi(vtcode3) - vf %lo(vtcode3)(a0) - la a5,dest - vsd vx5,a5 - fence - - ld a1,0(a5) - li a2,4 - li TESTNUM,6 - bne a1,a2,fail - ld a1,8(a5) - li a2,3 - li TESTNUM,7 - bne a1,a2,fail - ld a1,16(a5) - li a2,2 - li TESTNUM,8 - bne a1,a2,fail - ld a1,24(a5) - li a2,1 - li TESTNUM,9 - bne a1,a2,fail - - j pass - -vtcode1: - beq x2, x2, end - add x2,x2,x3 -end: add x2, x3, x3 - stop - -vtcode2: - blt x4, x5, end2 - add x4, x0, x0 -end2: add x4, x4, x0 - stop - -vtcode3: - bge x5, x0, end3 - add x5, x0, x0 -end3: add x5, x5,x0 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .dword 1 - .dword 2 - .dword 3 - .dword 4 -src2: - .dword 4 - .dword 3 - .dword 2 - .dword 1 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - -RVTEST_DATA_END diff --git a/isa/rv64uv/vvadd_d.S b/isa/rv64uv/vvadd_d.S deleted file mode 100644 index d17e6e0..0000000 --- a/isa/rv64uv/vvadd_d.S +++ /dev/null @@ -1,133 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# vvadd_d.S -#----------------------------------------------------------------------------- -# -# Test vvadd d. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - la a3,src1 - la a4,src2 - vld vx2,a3 - vld vx3,a4 - lui a0,%hi(vtcode1) - vf %lo(vtcode1)(a0) - la a5,dest - vsd vx2,a5 - fence - - ld a1,0(a5) - li a2,5 - li TESTNUM,2 - bne a1,a2,fail - ld a1,8(a5) - li TESTNUM,3 - bne a1,a2,fail - ld a1,16(a5) - li TESTNUM,4 - bne a1,a2,fail - ld a1,24(a5) - li TESTNUM,5 - bne a1,a2,fail - - la a3,src1 - vld vx4,a3 - lui a0,%hi(vtcode2) - vf %lo(vtcode2)(a0) - la a5,dest - vsd vx4,a5 - fence - - ld a1,0(a5) - li a2,1 - li TESTNUM,6 - bne a1,a2,fail - ld a1,8(a5) - li a2,2 - li TESTNUM,7 - bne a1,a2,fail - ld a1,16(a5) - li a2,3 - li TESTNUM,8 - bne a1,a2,fail - ld a1,24(a5) - li a2,4 - li TESTNUM,9 - bne a1,a2,fail - - la a3,src2 - vld vx5,a3 - lui a0,%hi(vtcode3) - vf %lo(vtcode3)(a0) - la a5,dest - vsd vx5,a5 - fence - - ld a1,0(a5) - li a2,4 - li TESTNUM,6 - bne a1,a2,fail - ld a1,8(a5) - li a2,3 - li TESTNUM,7 - bne a1,a2,fail - ld a1,16(a5) - li a2,2 - li TESTNUM,8 - bne a1,a2,fail - ld a1,24(a5) - li a2,1 - li TESTNUM,9 - bne a1,a2,fail - - j pass - -vtcode1: - add x2,x2,x3 - stop - -vtcode2: - add a0,a0,x0 - stop - -vtcode3: - add a1,a1,x0 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .dword 1 - .dword 2 - .dword 3 - .dword 4 -src2: - .dword 4 - .dword 3 - .dword 2 - .dword 1 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - -RVTEST_DATA_END diff --git a/isa/rv64uv/vvadd_fd.S b/isa/rv64uv/vvadd_fd.S deleted file mode 100644 index 6a7c4b2..0000000 --- a/isa/rv64uv/vvadd_fd.S +++ /dev/null @@ -1,79 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# vvadd_fd.S -#----------------------------------------------------------------------------- -# -# Test vvadd fd. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 32,32 - li a3,4 - vsetvl a3,a3 - - la a3,src1 - la a4,src2 - vfld vf2,a3 - vfld vf3,a4 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a5,dest - vfsd vf2,a5 - fence - la a6,result - ld a1,0(a5) - ld a2,0(a6) - li TESTNUM,2 - bne a1,a2,fail - ld a1,8(a5) - li TESTNUM,3 - bne a1,a2,fail - ld a1,16(a5) - li TESTNUM,4 - bne a1,a2,fail - ld a1,24(a5) - li TESTNUM,5 - bne a1,a2,fail - j pass - -vtcode: - fadd.d f2,f2,f3 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .double 0.1 - .double 0.2 - .double 0.3 - .double 0.4 -src2: - .double 0.4 - .double 0.3 - .double 0.2 - .double 0.1 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe -result: - .double 0.5 - .double 0.5 - .double 0.5 - .double 0.5 - -RVTEST_DATA_END diff --git a/isa/rv64uv/vvadd_fw.S b/isa/rv64uv/vvadd_fw.S deleted file mode 100644 index 2dcf9ff..0000000 --- a/isa/rv64uv/vvadd_fw.S +++ /dev/null @@ -1,79 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# vvadd_fw.S -#----------------------------------------------------------------------------- -# -# Test vvadd fw. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 32,32 - li a3,4 - vsetvl a3,a3 - - la a3,src1 - la a4,src2 - vflw vf2,a3 - vflw vf3,a4 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a5,dest - vfsw vf2,a5 - fence - la a6,result - lw a1,0(a5) - lw a2,0(a6) - li TESTNUM,2 - bne a1,a2,fail - lw a1,4(a5) - li TESTNUM,3 - bne a1,a2,fail - lw a1,8(a5) - li TESTNUM,4 - bne a1,a2,fail - lw a1,12(a5) - li TESTNUM,5 - bne a1,a2,fail - j pass - -vtcode: - fadd.s f2,f2,f3 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .single 0.1 - .single 0.2 - .single 0.3 - .single 0.4 -src2: - .single 0.4 - .single 0.3 - .single 0.2 - .single 0.1 -dest: - .word 0xdeadbeef - .word 0xdeadbeef - .word 0xdeadbeef - .word 0xdeadbeef -result: - .single 0.5 - .single 0.5 - .single 0.5 - .single 0.5 - -RVTEST_DATA_END diff --git a/isa/rv64uv/vvadd_packed.S b/isa/rv64uv/vvadd_packed.S deleted file mode 100644 index fb02a72..0000000 --- a/isa/rv64uv/vvadd_packed.S +++ /dev/null @@ -1,107 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# vvadd_packed.S -#----------------------------------------------------------------------------- -# -# Test packed half-precision vvadd -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - li x1, 12 # number of test elements - move x10, x1 - vsetucfg x2, 0x2 - vsetcfg x2, 3, 1 -loop: - vsetvl x4, x1 - la x2, addr - vmsv vx1, x2 - la x3, test - vf 0(x3) - sub x1, x1, x4 - bnez x1, loop - fence - j check - -enable_accel: - csrr x2, status - ori x2, x2, 0x100 - csrw status, x2 - # test if set - csrr x2, status - andi x2, x2, 0x100 - beqz x2, fail - ret - -enable_fp: - csrr x2, status - ori x2, x2, 0x10 - csrw status, x2 - # test if set - csrr x2, status - andi x2, x2, 0x10 - beqz x2, fail - ret - -test: - utidx x2 - slli x2, x2, 2 - add x1, x1, x2 - flh f0, 0(x1) - fmul.h f0, f0, f0 - fsh f0, 0(x1) - stop - -check: - la x2, addr - la x4, expc - -check_loop: - lw x3, 0(x4) - lw x1, 0(x2) - bne x1, x3, fail - addi x10, x10, -1 - addi x4, x4, 0x4 - addi x2, x2, 0x4 - bnez x10, check_loop - j pass - - TEST_PASSFAIL - -.data -RVTEST_DATA_BEGIN - - TEST_DATA - -addr: .word 0x4000 - .word 0x4400 - .word 0x4800 - .word 0x5000 - .word 0x4001 - .word 0x4401 - .word 0x4801 - .word 0x5001 - .word 0x4002 - .word 0x4402 - .word 0x4802 - .word 0x5002 - -expc: .word 0x4400 - .word 0x4c00 - .word 0x5400 - .word 0x6400 - .word 0x4402 - .word 0x4c02 - .word 0x5402 - .word 0x6402 - .word 0x4404 - .word 0x4c04 - .word 0x5404 - .word 0x6404 - -RVTEST_DATA_END diff --git a/isa/rv64uv/vvadd_w.S b/isa/rv64uv/vvadd_w.S deleted file mode 100644 index 842f265..0000000 --- a/isa/rv64uv/vvadd_w.S +++ /dev/null @@ -1,88 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# vvadd_w.S -#----------------------------------------------------------------------------- -# -# Test vvadd w. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 32,0 - li a3,9 - vsetvl a3,a3 - - la a3,src1 - la a4,src2 - vlw vx2,a3 - vlw vx3,a4 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a5,dest - vsw vx2,a5 - fence - lw a1,0(a5) - li a2,10 - li TESTNUM,2 - bne a1,a2,fail - lw a1,4(a5) - li TESTNUM,3 - bne a1,a2,fail - lw a1,8(a5) - li TESTNUM,4 - bne a1,a2,fail - lw a1,12(a5) - li TESTNUM,5 - bne a1,a2,fail - j pass - -vtcode: - addw x2,x2,x3 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .word 1 - .word 2 - .word 3 - .word 4 - .word 5 - .word 6 - .word 7 - .word 8 - .word 9 -src2: - .word 9 - .word 8 - .word 7 - .word 6 - .word 5 - .word 4 - .word 3 - .word 2 - .word 1 -dest: - .word 0xdeadbeef - .word 0xdeadbeef - .word 0xdeadbeef - .word 0xdeadbeef - .word 0xdeadbeef - .word 0xdeadbeef - .word 0xdeadbeef - .word 0xdeadbeef - .word 0xdeadbeef - -RVTEST_DATA_END diff --git a/isa/rv64uv/vvmul_d.S b/isa/rv64uv/vvmul_d.S deleted file mode 100644 index 433b80e..0000000 --- a/isa/rv64uv/vvmul_d.S +++ /dev/null @@ -1,76 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# vvmul_d.S -#----------------------------------------------------------------------------- -# -# Test vvmul d. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - vsetcfg 32,0 - li a3,4 - vsetvl a3,a3 - - la a3,src1 - la a4,src2 - vld vx2,a3 - vld vx3,a4 - lui a0,%hi(vtcode) - vf %lo(vtcode)(a0) - la a5,dest - vsd vx2,a5 - fence - ld a1,0(a5) - li a2,4 - li TESTNUM,2 - bne a1,a2,fail - ld a1,8(a5) - li a2,6 - li TESTNUM,3 - bne a1,a2,fail - ld a1,16(a5) - li a2,6 - li TESTNUM,4 - bne a1,a2,fail - ld a1,24(a5) - li a2,4 - li TESTNUM,5 - bne a1,a2,fail - j pass - -vtcode: - mul x2,x2,x3 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .dword 1 - .dword 2 - .dword 3 - .dword 4 -src2: - .dword 4 - .dword 3 - .dword 2 - .dword 1 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - -RVTEST_DATA_END diff --git a/isa/rv64uv/wakeup.S b/isa/rv64uv/wakeup.S deleted file mode 100644 index 357682a..0000000 --- a/isa/rv64uv/wakeup.S +++ /dev/null @@ -1,160 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# wakeup.S -#----------------------------------------------------------------------------- -# -# Test wakeup. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UV -RVTEST_CODE_BEGIN - - # make sure these don't choke at the beginning - fence - fence rw,io - fence io,rw - - # this shouldn't go through since app vl is zero - la a3,src1 - la a4,src2 - vld vx2,a3 - vld vx3,a4 - lui a0,%hi(vtcode1) - vf %lo(vtcode1)(a0) - la a5,dest - vsd vx2,a5 - fence - - ld a1,0(a5) - li a2,0xdeadbeefcafebabe - li TESTNUM,2 - bne a1,a2,fail - ld a1,8(a5) - li TESTNUM,3 - bne a1,a2,fail - ld a1,16(a5) - li TESTNUM,4 - bne a1,a2,fail - ld a1,24(a5) - li TESTNUM,5 - bne a1,a2,fail - - # check default hw vector length, which is 32 - li a3, 32 - vsetvl a3, a3 - li a0, 32 - li TESTNUM, 6 - bne a3, a0, fail - - li a3, 33 - vsetvl a3, a3 - li a0, 32 - li TESTNUM, 7 - bne a3, a0, fail - - li a3, 31 - vsetvl a3, a3 - li a0, 31 - li TESTNUM, 8 - bne a3, a0, fail - - # now do some vector stuff without vsetcfg - vsetvl x0, x0 - - li a3, 4 - la a4,src1 - la a5,src2 - vsetvl a3, a3 - vld vx2,a4 - vld vx3,a5 - lui a0,%hi(vtcode1) - vf %lo(vtcode1)(a0) - la a5,dest - vsd vx2,a5 - fence - - ld a1,0(a5) - li a2,5 - li TESTNUM,9 - bne a1,a2,fail - ld a1,8(a5) - li TESTNUM,10 - bne a1,a2,fail - ld a1,16(a5) - li TESTNUM,11 - bne a1,a2,fail - ld a1,24(a5) - li TESTNUM,12 - bne a1,a2,fail - - # initialize dest memory - li a3, 0xdeadbeefcafebabe - sd a3, 0(a5) - sd a3, 8(a5) - sd a3, 16(a5) - sd a3, 24(a5) - - # test app vl zero again - li a3, 0 - vsetvl a3, a3 - - la a3,src1 - la a4,src2 - vld vx2,a3 - vld vx3,a4 - lui a0,%hi(vtcode1) - vf %lo(vtcode1)(a0) - la a5,dest - vsd vx2,a5 - fence - - ld a1,0(a5) - li a2,0xdeadbeefcafebabe - li TESTNUM,13 - bne a1,a2,fail - ld a1,8(a5) - li TESTNUM,14 - bne a1,a2,fail - ld a1,16(a5) - li TESTNUM,15 - bne a1,a2,fail - ld a1,24(a5) - li TESTNUM,16 - bne a1,a2,fail - - j pass - -vtcode1: - add x2,x2,x3 - stop - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -src1: - .dword 1 - .dword 2 - .dword 3 - .dword 4 -src2: - .dword 4 - .dword 3 - .dword 2 - .dword 1 -dest: - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - .dword 0xdeadbeefcafebabe - -RVTEST_DATA_END diff --git a/mt/Makefile b/mt/Makefile index 9829927..e4a8bfd 100755 --- a/mt/Makefile +++ b/mt/Makefile @@ -77,7 +77,7 @@ bmarks = $(bmarks_vvadd) $(bmarks_matmul) RISCV_PREFIX=riscv64-unknown-elf- RISCV_GCC = $(RISCV_PREFIX)gcc -RISCV_GCC_OPTS = -Wa,-march=RVIMAFDXhwacha -std=gnu99 -O2 -ffast-math +RISCV_GCC_OPTS = -std=gnu99 -O2 -ffast-math RISCV_LINK = $(RISCV_GCC) -T $(common)/test.ld $(incs) RISCV_LINK_OPTS = -nostdlib -nostartfiles -ffast-math -lc RISCV_OBJDUMP = $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data -- 2.30.2