From 7e9be87de1f3ed1a07b4d90f059ea2d1882fda6b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 2 Oct 2018 08:32:34 +0100 Subject: [PATCH] add rv64ud sv fadd test, shows flaw in loop for 3-arg operands --- isa/Makefile | 1 + isa/macros/simplev/sv_test_macros.h | 13 ++++++ isa/rv64ud/Makefrag.sv | 11 +++++ isa/rv64ud/sv_fadd.S | 70 +++++++++++++++++++++++++++++ 4 files changed, 95 insertions(+) create mode 100644 isa/rv64ud/Makefrag.sv create mode 100644 isa/rv64ud/sv_fadd.S diff --git a/isa/Makefile b/isa/Makefile index a3a5ee5..4411cce 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -14,6 +14,7 @@ include $(src_dir)/rv64um/Makefrag include $(src_dir)/rv64ua/Makefrag include $(src_dir)/rv64uf/Makefrag include $(src_dir)/rv64ud/Makefrag +include $(src_dir)/rv64ud/Makefrag.sv include $(src_dir)/rv64si/Makefrag include $(src_dir)/rv64mi/Makefrag endif diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h index 97bb950..23feaa1 100644 --- a/isa/macros/simplev/sv_test_macros.h +++ b/isa/macros/simplev/sv_test_macros.h @@ -26,6 +26,19 @@ la x1, from; \ lw reg, offs(x1) +#define SV_FLD_DATA( reg, from, offs ) \ + la x1, from; \ + fld reg, offs(x1) + #define TEST_SV_IMM( reg, imm ) \ li x1, imm; \ bne reg, x1, fail + +#define TEST_SV_FD( flags, freg, from, offs ) \ + fsflags x2, x0; \ + li x1, flags; \ + bne x2, x1, fail; \ + la x1, from; \ + ld x1, offs(x1); \ + fmv.x.d x2, freg; \ + bne x2, x1, fail diff --git a/isa/rv64ud/Makefrag.sv b/isa/rv64ud/Makefrag.sv new file mode 100644 index 0000000..6407239 --- /dev/null +++ b/isa/rv64ud/Makefrag.sv @@ -0,0 +1,11 @@ +#======================================================================= +# Makefrag for rv64ud tests +#----------------------------------------------------------------------- + +rv64ud_sv_tests = \ + sv_fadd \ + +rv64ud_p_tests = $(addprefix rv64ud-p-, $(rv64ud_sv_tests)) +rv64ud_v_tests = $(addprefix rv64ud-v-, $(rv64ud_sv_tests)) + +spike_tests += $(rv64ud_p_tests) $(rv64ud_v_tests) diff --git a/isa/rv64ud/sv_fadd.S b/isa/rv64ud/sv_fadd.S new file mode 100644 index 0000000..f456119 --- /dev/null +++ b/isa/rv64ud/sv_fadd.S @@ -0,0 +1,70 @@ +#include "riscv_test.h" +#include "sv_test_macros.h" + +RVTEST_RV64UF + + +# SV test: vector-vector fadd +# +# sets up x3 and x4 with data, sets VL to 2, and carries out +# an "add 1 to x3". which actually means "add 1 to x3 *AND* add 1 to x4" + +# Test code region. +RVTEST_CODE_BEGIN # Start of test code. + + SV_FLD_DATA( f1, testdata , 0) + SV_FLD_DATA( f2, testdata+8 , 0) + SV_FLD_DATA( f3, testdata+16, 0) + SV_FLD_DATA( f4, testdata+24, 0) + SV_FLD_DATA( f5, testdata+32, 0) + SV_FLD_DATA( f6, testdata+40, 0) + SV_FLD_DATA( f7, testdata+48, 0) + SV_FLD_DATA( f8, testdata+56, 0) + + SET_SV_MVL(2) + SET_SV_CSR(0, 2, 0, 2, 1, 0) + SET_SV_VL(2) + + fadd.d f2, f2, f6; + + CLR_SV_CSRS() + SET_SV_VL(0) + SET_SV_MVL(0) + + TEST_SV_FD(0, f1, testdata+64, 0) + TEST_SV_FD(0, f2, testdata+72, 0) + TEST_SV_FD(0, f3, testdata+80, 0) + TEST_SV_FD(0, f4, testdata+88, 0) + + RVTEST_PASS # Signal success. +fail: + RVTEST_FAIL +RVTEST_CODE_END # End of test code. + +# Input data section. +# This section is optional, and this data is NOT saved in the output. +.data + .align 3 +testdata: + .double 1001.0 + .double 41.0 + .double 42.0 + .double 1002.0 + .double 1001.0 + .double 1.0 + .double 2.0 + .double 1002.0 + .double 1001.0 + .double 42.0 + .double 44.0 + .double 1002.0 + +# Output data section. +RVTEST_DATA_BEGIN # Start of test output data region. + .align 3 +result: + .dword -1 + .dword -1 + .dword -1 +RVTEST_DATA_END # End of test output data region. + -- 2.30.2