From a924a13af9980c1c6f2c90b66856f9d20bf1daa3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 27 Jun 2019 12:51:29 +0100 Subject: [PATCH] add subvl add-immediate test --- isa/macros/simplev/sv_test_macros.h | 3 ++ isa/rv64ui/Makefrag.sv | 1 + isa/rv64ui/sv_addi_subvl.S | 60 +++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+) create mode 100644 isa/rv64ui/sv_addi_subvl.S diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h index 2242235..725ed9e 100644 --- a/isa/macros/simplev/sv_test_macros.h +++ b/isa/macros/simplev/sv_test_macros.h @@ -67,6 +67,9 @@ // pass in x0 here. #define SET_SV_VL( val ) csrrwi x0, 0x4f0, (val-1) +// set sub-vector length +#define SET_SV_SUBVL( val ) csrrwi x0, 0x4f4, val + #define SV_LD_DATA( reg, from, offs ) \ la x1, from; \ lw reg, offs(x1) diff --git a/isa/rv64ui/Makefrag.sv b/isa/rv64ui/Makefrag.sv index c7130d0..5f1da93 100644 --- a/isa/rv64ui/Makefrag.sv +++ b/isa/rv64ui/Makefrag.sv @@ -9,6 +9,7 @@ rv64ui_sv_tests = \ sv_addi_vector_vector \ sv_addi_predicated \ sv_add_elwidth \ + sv_addi_subvl \ sv_addw_elwidth \ sv_sraw_elwidth \ sv_ld_elwidth \ diff --git a/isa/rv64ui/sv_addi_subvl.S b/isa/rv64ui/sv_addi_subvl.S new file mode 100644 index 0000000..a707db8 --- /dev/null +++ b/isa/rv64ui/sv_addi_subvl.S @@ -0,0 +1,60 @@ +#include "riscv_test.h" +#include "sv_test_macros.h" + +RVTEST_RV64U # Define TVM used by program. + + +# SV test: vector-vector add +# +# sets up x3 and x4 with data, sets VL to 2, and carries out +# an "add 1 to x3". which actually means "add 1 to x3 *AND* add 1 to x4" + +# Test code region. +RVTEST_CODE_BEGIN # Start of test code. + + SV_LD_DATA( x2, testdata , 0) + SV_LD_DATA( x3, testdata+8 , 0) + SV_LD_DATA( x4, testdata+16, 0) + SV_LD_DATA( x5, testdata+24, 0) + + SET_SV_MVL(1) + SET_SV_CSR(1, 3, 0, 3, 1) + SET_SV_VL(1) + SET_SV_SUBVL(2) + + addi x3, x3, 1 + + CLR_SV_CSRS() + SET_SV_VL(1) + SET_SV_MVL(1) + SET_SV_SUBVL(1) + + TEST_SV_IMM(x2, 1001) # should not be modified + TEST_SV_IMM(x3, 42) + TEST_SV_IMM(x4, 43) + TEST_SV_IMM(x5, 1002) # should not be modified + + RVTEST_PASS # Signal success. +fail: + RVTEST_FAIL +RVTEST_CODE_END # End of test code. + +# Input data section. +# This section is optional, and this data is NOT saved in the output. +.data + .align 3 +testdata: + .dword 1001 + .dword 41 + .dword 42 + .dword 1002 + +# Output data section. +RVTEST_DATA_BEGIN # Start of test output data region. + .align 3 +result: + .dword -1 + .dword -1 + .dword -1 +RVTEST_DATA_END # End of test output data region. + -- 2.30.2