From ba03aaffa68160673b33d1b25e7011d03ffcad55 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 7 Oct 2018 04:50:37 +0100 Subject: [PATCH] add s.swsp sv test --- isa/rv64uc/Makefrag.sv | 1 + isa/rv64uc/sv_c_swsp.S | 70 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 71 insertions(+) create mode 100644 isa/rv64uc/sv_c_swsp.S diff --git a/isa/rv64uc/Makefrag.sv b/isa/rv64uc/Makefrag.sv index a4a2716..a50ab21 100644 --- a/isa/rv64uc/Makefrag.sv +++ b/isa/rv64uc/Makefrag.sv @@ -6,6 +6,7 @@ rv64uc_sv_tests = \ sv_c_mv \ sv_c_mv_predication \ sv_c_lwsp \ + sv_c_swsp \ rv64uc_p_tests = $(addprefix rv64uc-p-, $(rv64uc_sv_tests)) rv64uc_v_tests = $(addprefix rv64uc-v-, $(rv64uc_sv_tests)) diff --git a/isa/rv64uc/sv_c_swsp.S b/isa/rv64uc/sv_c_swsp.S new file mode 100644 index 0000000..11d0229 --- /dev/null +++ b/isa/rv64uc/sv_c_swsp.S @@ -0,0 +1,70 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rvc.S +#----------------------------------------------------------------------------- +# +# Test RVC corner cases. +# + +#include "riscv_test.h" +#include "sv_test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + .align 2 + .option push + .option norvc + + li a2, 1000; + li a3, 1001; + + SET_SV_MVL(2) + SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1, 0), + SV_REG_CSR(1, 2, 0, 2, 1, 0) ) + SET_SV_VL(2) + + mv a1, sp + la sp, data; + + .option push; + .option rvc; + .align 2; + c.swsp a2, 0(sp); + #lw a2, 0(sp); + .option pop + + + SET_SV_VL(0) + CLR_SV_CSRS() + SET_SV_MVL(0) + + mv sp, a1 + + li a2, 0; + li a3, 0; + + la a2, data; + lw a4, 0(a2); + lw a5, 4(a2); + + TEST_SV_IMM(a4, 1000) + TEST_SV_IMM(a5, 1001) + + .option pop + + RVTEST_PASS # Signal success. +fail: + RVTEST_FAIL + +RVTEST_CODE_END # End of test code. + + .data +data: + .word 0; + .word 0; + +RVTEST_DATA_BEGIN + +RVTEST_DATA_END -- 2.30.2