From bf9f76229e6055d71cc33f71249ce02ce6c3f566 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 11 Nov 2018 20:28:58 +0000
Subject: [PATCH] redirect c_lwsp / c_swsp to x28

---
 isa/rv64uc/sv_c_lwsp.S | 46 ++++++++++++++++++++++++++++++++++++------
 isa/rv64uc/sv_c_swsp.S | 44 +++++++++++++++++++++++++++++++++++++---
 2 files changed, 81 insertions(+), 9 deletions(-)

diff --git a/isa/rv64uc/sv_c_lwsp.S b/isa/rv64uc/sv_c_lwsp.S
index 38dcaa2..a642203 100644
--- a/isa/rv64uc/sv_c_lwsp.S
+++ b/isa/rv64uc/sv_c_lwsp.S
@@ -17,9 +17,43 @@ RVTEST_CODE_BEGIN
   .option push
   .option norvc
 
-        li          a2, 0 
-        li          a3, 0 
-        li          a4, 0 
+        li          a2, 0
+        li          a3, 0
+        li          a4, 0
+
+        SET_SV_MVL(3)
+        SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1),
+                      SV_REG_CSR(1, 2, 0, 28, 1) )
+        SET_SV_VL(3)
+
+  # store addr of data in x28 because CSR redirects x2 to x28
+  # and c.lwsp is an element-offset (if isvec=true that is)
+  la x28, data;
+
+  .option push;
+  .option rvc;
+  .align 2;
+  c.lwsp a2, 0(sp); # SP is actually redirected to x28!
+  .option pop
+
+
+        SET_SV_VL(1)
+        CLR_SV_CSRS()
+        SET_SV_MVL(1)
+
+        TEST_SV_IMM(a2, 1001)
+        TEST_SV_IMM(a3, 1002)
+        TEST_SV_IMM(a4, 1005)
+
+  .option pop
+
+  .align 2
+  .option push
+  .option norvc
+
+        li          a2, 0
+        li          a3, 0
+        li          a4, 0
 
         SET_SV_MVL(3)
         SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1),
@@ -30,8 +64,8 @@ RVTEST_CODE_BEGIN
   la sp, data;
 
   .option push;
-  .option rvc; 
-  .align 2; 
+  .option rvc;
+  .align 2;
   c.lwsp a2, 0(sp);
   #lw a2, 0(sp);
   .option pop
@@ -43,7 +77,7 @@ RVTEST_CODE_BEGIN
 
   mv sp, a1
 
-        TEST_SV_IMM(a2, 1001) 
+        TEST_SV_IMM(a2, 1001)
         TEST_SV_IMM(a3, 1002)
         TEST_SV_IMM(a4, 1005)
 
diff --git a/isa/rv64uc/sv_c_swsp.S b/isa/rv64uc/sv_c_swsp.S
index 622ca9e..64d38cd 100644
--- a/isa/rv64uc/sv_c_swsp.S
+++ b/isa/rv64uc/sv_c_swsp.S
@@ -13,6 +13,44 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  .align 2
+  .option push
+  .option norvc
+
+        li          a2, 1000;
+        li          a3, 1001;
+        li          a4, 1004;
+
+        SET_SV_MVL(3)
+        SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1),
+                      SV_REG_CSR(1, 2, 0, 28, 1) )
+        SET_SV_VL(3)
+
+  # CSR redirects SP (x2) to x28
+  la x28, data;
+
+  .option push;
+  .option rvc;
+  .align 2;
+  c.swsp a2, 0(sp); # not SP, actually x28!
+  .option pop
+
+
+        SET_SV_VL(1)
+        CLR_SV_CSRS()
+        SET_SV_MVL(1)
+
+  la a2, data;
+  lw a4, 0(a2);
+  lw a5, 4(a2);
+  lw a6, 8(a2);
+
+        TEST_SV_IMM(a4, 1000)
+        TEST_SV_IMM(a5, 1001)
+        TEST_SV_IMM(a6, 1004)
+
+  .option pop
+
   .align 2
   .option push
   .option norvc
@@ -30,8 +68,8 @@ RVTEST_CODE_BEGIN
   la sp, data;
 
   .option push;
-  .option rvc; 
-  .align 2; 
+  .option rvc;
+  .align 2;
   c.swsp a2, 0(sp);
   #lw a2, 0(sp);
   .option pop
@@ -48,7 +86,7 @@ RVTEST_CODE_BEGIN
   lw a5, 4(a2);
   lw a6, 8(a2);
 
-        TEST_SV_IMM(a4, 1000) 
+        TEST_SV_IMM(a4, 1000)
         TEST_SV_IMM(a5, 1001)
         TEST_SV_IMM(a6, 1004)
 
-- 
2.30.2