From c8096ab01f92e8fd68b2077e5c6c58a46eae3675 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 4 Oct 2018 15:18:20 +0100
Subject: [PATCH] add sv c.mv twin-predication unit test

---
 isa/Makefile           |  1 +
 isa/rv64uc/Makefrag.sv | 11 ++++++++
 isa/rv64uc/sv_c_mv.S   | 64 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 76 insertions(+)
 create mode 100644 isa/rv64uc/Makefrag.sv
 create mode 100644 isa/rv64uc/sv_c_mv.S

diff --git a/isa/Makefile b/isa/Makefile
index 4411cce..40e57a9 100644
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -10,6 +10,7 @@ ifeq ($(XLEN),64)
 include $(src_dir)/rv64ui/Makefrag
 include $(src_dir)/rv64ui/Makefrag.sv
 include $(src_dir)/rv64uc/Makefrag
+include $(src_dir)/rv64uc/Makefrag.sv
 include $(src_dir)/rv64um/Makefrag
 include $(src_dir)/rv64ua/Makefrag
 include $(src_dir)/rv64uf/Makefrag
diff --git a/isa/rv64uc/Makefrag.sv b/isa/rv64uc/Makefrag.sv
new file mode 100644
index 0000000..e35fb34
--- /dev/null
+++ b/isa/rv64uc/Makefrag.sv
@@ -0,0 +1,11 @@
+#=======================================================================
+# Makefrag for rv64uc tests
+#-----------------------------------------------------------------------
+
+rv64uc_sv_tests = \
+	sv_c_mv \
+
+rv64uc_p_tests = $(addprefix rv64uc-p-, $(rv64uc_sv_tests))
+rv64uc_v_tests = $(addprefix rv64uc-v-, $(rv64uc_sv_tests))
+
+spike_tests += $(rv64uc_p_tests) $(rv64uc_v_tests)
diff --git a/isa/rv64uc/sv_c_mv.S b/isa/rv64uc/sv_c_mv.S
new file mode 100644
index 0000000..a10d33c
--- /dev/null
+++ b/isa/rv64uc/sv_c_mv.S
@@ -0,0 +1,64 @@
+#include "riscv_test.h"
+#include "sv_test_macros.h"
+
+RVTEST_RV64U        # Define TVM used by program.
+
+
+# SV test: vector-vector add different rd and rs1
+#
+# sets up x6 and x7 with data, sets VL to 2, and carries out
+# an "x3 = 1 + x6".  which actually means "x3 = 1 + x6 *AND* x4 = 1 + x7"
+
+# Test code region.
+RVTEST_CODE_BEGIN   # Start of test code.
+
+        .option norvc
+
+        SV_LD_DATA( x5, testdata+0 , 0)
+        SV_LD_DATA( x6, testdata+8, 0)
+        SV_LD_DATA( x7, testdata+16, 0)
+
+        li          x2, 0 # deliberately set x3 to 0 (target of add)
+        li          x3, 0 # deliberately set x4 to 0
+        li          x4, 0 # deliberately set x4 to 0
+
+        SET_SV_MVL(3)
+        SET_SV_2CSRS( SV_REG_CSR(1, 2, 0, 2, 1, 0),
+                      SV_REG_CSR(1, 5, 0, 5, 1, 0) )
+        SET_SV_VL(3)
+
+        .option rvc
+        c.mv    x2, x5
+        .option norvc
+
+        SET_SV_VL(0)
+        CLR_SV_CSRS()
+        SET_SV_MVL(0)
+
+        TEST_SV_IMM(x2, 1001) # should not be modified
+        TEST_SV_IMM(x3, 41)
+        TEST_SV_IMM(x4, 42)
+
+        RVTEST_PASS           # Signal success.
+fail:
+        RVTEST_FAIL
+RVTEST_CODE_END     # End of test code.
+
+# Input data section.
+# This section is optional, and this data is NOT saved in the output.
+.data
+        .align 3
+testdata:
+        .dword 1001
+        .dword 41
+        .dword 42
+
+# Output data section.
+RVTEST_DATA_BEGIN   # Start of test output data region.
+        .align 3
+result:
+        .dword -1
+        .dword -1
+        .dword -1
+RVTEST_DATA_END     # End of test output data region.
+
-- 
2.30.2