From e0e74d76a902e19e5f8c097c3ce4a0244515e000 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 11 Nov 2018 05:21:57 +0000 Subject: [PATCH] add some comments to the macros --- isa/macros/simplev/sv_test_macros.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h index f725de9..543f0c3 100644 --- a/isa/macros/simplev/sv_test_macros.h +++ b/isa/macros/simplev/sv_test_macros.h @@ -29,6 +29,8 @@ li x1, SV_SHAPE_CSR( xd, yd, zd, offs, permute); \ csrrw x0, 0x4f8, x1 +// series of macros that set one, two or three register (or predicate) +// key-value table entries that alter the behaviour of the registers #define SET_SV_CSR( type, regkey, elwidth, regidx, isvec) \ li x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \ csrrw x0, 0x4c0, x1 @@ -53,10 +55,16 @@ li x1, c1 | ((c2)<<16U); \ csrrw x0, 0x4c8, x1 +// clears the 2 CSRs set above #define CLR_SV_CSRS( ) csrrw x0, 0x4c0, 0 #define CLR_SV_PRED_CSRS( ) csrrw x0, 0x4c8, 0 +// set maximum vector length. #define SET_SV_MVL( val ) csrrwi x0, 0x4f1, (val-1) + +// set actual vector length: normally that would +// be vl = xN = min(mvl, min(vl, xN) however we +// pass in x0 here. #define SET_SV_VL( val ) csrrwi x0, 0x4f0, (val-1) #define SV_LD_DATA( reg, from, offs ) \ -- 2.30.2