From e2e75e127edd203d4c31b0ff5d9dc6170e42d71b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 16 Oct 2018 23:41:20 +0100 Subject: [PATCH] modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1) --- isa/macros/simplev/sv_test_macros.h | 4 +- isa/rv64uc/Makefrag.sv | 1 + isa/rv64uc/sv_c_beqz.S | 74 +++++++++++++++++++++++++++++ isa/rv64uc/sv_c_lwsp.S | 4 +- isa/rv64uc/sv_c_lwsp_predication.S | 4 +- isa/rv64uc/sv_c_mv.S | 4 +- isa/rv64uc/sv_c_mv_predication.S | 4 +- isa/rv64uc/sv_c_swsp.S | 4 +- isa/rv64ud/sv_fadd.S | 4 +- isa/rv64ui/sv_addi.S | 4 +- isa/rv64ui/sv_addi_predicated.S | 4 +- isa/rv64ui/sv_addi_redirect.S | 4 +- isa/rv64ui/sv_addi_scalar_src.S | 4 +- isa/rv64ui/sv_addi_vector_vector.S | 4 +- isa/rv64ui/sv_beq.S | 4 +- 15 files changed, 101 insertions(+), 26 deletions(-) create mode 100644 isa/rv64uc/sv_c_beqz.S diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h index b3b06c0..a480bd6 100644 --- a/isa/macros/simplev/sv_test_macros.h +++ b/isa/macros/simplev/sv_test_macros.h @@ -22,8 +22,8 @@ #define CLR_SV_CSRS( ) csrrw x0, 0x4c0, 0 #define CLR_SV_PRED_CSRS( ) csrrw x0, 0x4c8, 0 -#define SET_SV_MVL( val ) csrrwi x0, 0x4f2, val -#define SET_SV_VL( val ) csrrwi x0, 0x4f0, val +#define SET_SV_MVL( val ) csrrwi x0, 0x4f1, (val-1) +#define SET_SV_VL( val ) csrrwi x0, 0x4f0, (val-1) #define SV_LD_DATA( reg, from, offs ) \ la x1, from; \ diff --git a/isa/rv64uc/Makefrag.sv b/isa/rv64uc/Makefrag.sv index 52571ae..b97e6a0 100644 --- a/isa/rv64uc/Makefrag.sv +++ b/isa/rv64uc/Makefrag.sv @@ -8,6 +8,7 @@ rv64uc_sv_tests = \ sv_c_lwsp \ sv_c_lwsp_predication \ sv_c_swsp \ + sv_c_beqz \ rv64uc_p_tests = $(addprefix rv64uc-p-, $(rv64uc_sv_tests)) rv64uc_v_tests = $(addprefix rv64uc-v-, $(rv64uc_sv_tests)) diff --git a/isa/rv64uc/sv_c_beqz.S b/isa/rv64uc/sv_c_beqz.S new file mode 100644 index 0000000..8cf7fe8 --- /dev/null +++ b/isa/rv64uc/sv_c_beqz.S @@ -0,0 +1,74 @@ +#include "riscv_test.h" +#include "sv_test_macros.h" + +RVTEST_RV64U # Define TVM used by program. + + +# SV test: vector-vector add different rd and rs1 +# +# sets up x6 and x7 with data, sets VL to 2, and carries out +# an "x3 = 1 + x6". which actually means "x3 = 1 + x6 *AND* x4 = 1 + x7" + +# Test code region. +RVTEST_CODE_BEGIN # Start of test code. + + .align 2 + .option push + .option norvc + + li a3, 0x3 + li a4, 0x0 + + SET_SV_MVL(2) + SET_SV_2CSRS( SV_REG_CSR(1, 10, 0, 3, 1), + SV_REG_CSR(1, 0 , 0, 0, 1) ) + SET_SV_2PREDCSRS( \ + SV_PRED_CSR(1, 10, 0, 0, 13, 0), \ + SV_PRED_CSR(1, 0, 0, 0, 14, 0) );\ + + li x3, 0 + li x4, 0 + + SET_SV_VL(2) + + .option push; + .option rvc; + .align 2; + + c.beqz a0,here + + .option pop; + +here: + + CLR_SV_CSRS() + SET_SV_VL(1) + SET_SV_MVL(1) + + TEST_SV_IMM(a4, 0x3) + + .option pop; + RVTEST_PASS # Signal success. +fail: + RVTEST_FAIL +RVTEST_CODE_END # End of test code. + +# Input data section. +# This section is optional, and this data is NOT saved in the output. +.data + .align 3 +testdata: + .dword 1001 + .dword 0 + .dword 0 + .dword 1002 + +# Output data section. +RVTEST_DATA_BEGIN # Start of test output data region. + .align 3 +result: + .dword -1 + .dword -1 + .dword -1 +RVTEST_DATA_END # End of test output data region. + diff --git a/isa/rv64uc/sv_c_lwsp.S b/isa/rv64uc/sv_c_lwsp.S index e30d11a..38dcaa2 100644 --- a/isa/rv64uc/sv_c_lwsp.S +++ b/isa/rv64uc/sv_c_lwsp.S @@ -37,9 +37,9 @@ RVTEST_CODE_BEGIN .option pop - SET_SV_VL(0) + SET_SV_VL(1) CLR_SV_CSRS() - SET_SV_MVL(0) + SET_SV_MVL(1) mv sp, a1 diff --git a/isa/rv64uc/sv_c_lwsp_predication.S b/isa/rv64uc/sv_c_lwsp_predication.S index a0a2934..0885dd7 100644 --- a/isa/rv64uc/sv_c_lwsp_predication.S +++ b/isa/rv64uc/sv_c_lwsp_predication.S @@ -45,9 +45,9 @@ RVTEST_CODE_BEGIN .option pop - SET_SV_VL(0) + SET_SV_VL(1) CLR_SV_CSRS() - SET_SV_MVL(0) + SET_SV_MVL(1) mv sp, a6 diff --git a/isa/rv64uc/sv_c_mv.S b/isa/rv64uc/sv_c_mv.S index 11a042b..ce8dd41 100644 --- a/isa/rv64uc/sv_c_mv.S +++ b/isa/rv64uc/sv_c_mv.S @@ -31,9 +31,9 @@ RVTEST_CODE_BEGIN # Start of test code. c.mv x3, x6 .option norvc - SET_SV_VL(0) + SET_SV_VL(1) CLR_SV_CSRS() - SET_SV_MVL(0) + SET_SV_MVL(1) TEST_SV_IMM(x3, 1001) # should not be modified TEST_SV_IMM(x4, 41) diff --git a/isa/rv64uc/sv_c_mv_predication.S b/isa/rv64uc/sv_c_mv_predication.S index fc0bb74..7345de0 100644 --- a/isa/rv64uc/sv_c_mv_predication.S +++ b/isa/rv64uc/sv_c_mv_predication.S @@ -28,9 +28,9 @@ RVTEST_RV64U # Define TVM used by program. c.mv x3, x6; \ .option norvc; \ \ - SET_SV_VL(0); \ + SET_SV_VL(1); \ CLR_SV_CSRS(); \ - SET_SV_MVL(0); \ + SET_SV_MVL(1); \ \ TEST_SV_IMM(x3, expect1); \ TEST_SV_IMM(x4, expect2); \ diff --git a/isa/rv64uc/sv_c_swsp.S b/isa/rv64uc/sv_c_swsp.S index 7990707..622ca9e 100644 --- a/isa/rv64uc/sv_c_swsp.S +++ b/isa/rv64uc/sv_c_swsp.S @@ -37,9 +37,9 @@ RVTEST_CODE_BEGIN .option pop - SET_SV_VL(0) + SET_SV_VL(1) CLR_SV_CSRS() - SET_SV_MVL(0) + SET_SV_MVL(1) mv sp, a1 diff --git a/isa/rv64ud/sv_fadd.S b/isa/rv64ud/sv_fadd.S index 9057dff..5818a2b 100644 --- a/isa/rv64ud/sv_fadd.S +++ b/isa/rv64ud/sv_fadd.S @@ -29,8 +29,8 @@ RVTEST_CODE_BEGIN # Start of test code. fadd.d f2, f2, f6; CLR_SV_CSRS() - SET_SV_VL(0) - SET_SV_MVL(0) + SET_SV_VL(1) + SET_SV_MVL(1) TEST_SV_FD(0, f1, testdata+64, 0) TEST_SV_FD(0, f2, testdata+72, 0) diff --git a/isa/rv64ui/sv_addi.S b/isa/rv64ui/sv_addi.S index b73db85..c0fdb5a 100644 --- a/isa/rv64ui/sv_addi.S +++ b/isa/rv64ui/sv_addi.S @@ -24,8 +24,8 @@ RVTEST_CODE_BEGIN # Start of test code. addi x3, x3, 1 CLR_SV_CSRS() - SET_SV_VL(0) - SET_SV_MVL(0) + SET_SV_VL(1) + SET_SV_MVL(1) TEST_SV_IMM(x2, 1001) # should not be modified TEST_SV_IMM(x3, 42) diff --git a/isa/rv64ui/sv_addi_predicated.S b/isa/rv64ui/sv_addi_predicated.S index 46246ea..8bea7f8 100644 --- a/isa/rv64ui/sv_addi_predicated.S +++ b/isa/rv64ui/sv_addi_predicated.S @@ -20,8 +20,8 @@ RVTEST_RV64U # Define TVM used by program. addi x3, x3, 1; \ \ CLR_SV_CSRS(); \ - SET_SV_VL( 0); \ - SET_SV_MVL( 0); \ + SET_SV_VL( 1); \ + SET_SV_MVL( 1); \ \ TEST_SV_IMM( x2, 1001); \ TEST_SV_IMM( x3, expect1); \ diff --git a/isa/rv64ui/sv_addi_redirect.S b/isa/rv64ui/sv_addi_redirect.S index 74d41e0..aeb404d 100644 --- a/isa/rv64ui/sv_addi_redirect.S +++ b/isa/rv64ui/sv_addi_redirect.S @@ -26,8 +26,8 @@ RVTEST_CODE_BEGIN # Start of test code. addi x16, x16, 1 CLR_SV_CSRS() - SET_SV_VL(0) - SET_SV_MVL(0) + SET_SV_VL(1) + SET_SV_MVL(1) TEST_SV_IMM(x2, 1001) # should not be modified TEST_SV_IMM(x3, 42) diff --git a/isa/rv64ui/sv_addi_scalar_src.S b/isa/rv64ui/sv_addi_scalar_src.S index e17df23..edb0345 100644 --- a/isa/rv64ui/sv_addi_scalar_src.S +++ b/isa/rv64ui/sv_addi_scalar_src.S @@ -27,8 +27,8 @@ RVTEST_CODE_BEGIN # Start of test code. addi x3, x6, 1 # x3 = x6+1 *AND* x4 = x6+1 CLR_SV_CSRS() - SET_SV_VL(0) - SET_SV_MVL(0) + SET_SV_VL(1) + SET_SV_MVL(1) TEST_SV_IMM(x2, 1001) # should not be modified TEST_SV_IMM(x3, 42) diff --git a/isa/rv64ui/sv_addi_vector_vector.S b/isa/rv64ui/sv_addi_vector_vector.S index 8594ba7..b616e13 100644 --- a/isa/rv64ui/sv_addi_vector_vector.S +++ b/isa/rv64ui/sv_addi_vector_vector.S @@ -28,8 +28,8 @@ RVTEST_CODE_BEGIN # Start of test code. addi x3, x6, 1 CLR_SV_CSRS() - SET_SV_VL(0) - SET_SV_MVL(0) + SET_SV_VL(1) + SET_SV_MVL(1) TEST_SV_IMM(x2, 1001) # should not be modified TEST_SV_IMM(x3, 42) diff --git a/isa/rv64ui/sv_beq.S b/isa/rv64ui/sv_beq.S index 2c38e22..d012948 100644 --- a/isa/rv64ui/sv_beq.S +++ b/isa/rv64ui/sv_beq.S @@ -34,8 +34,8 @@ RVTEST_CODE_BEGIN # Start of test code. here: CLR_SV_CSRS() - SET_SV_VL(0) - SET_SV_MVL(0) + SET_SV_VL(1) + SET_SV_MVL(1) TEST_SV_IMM(a4, 0x3) -- 2.30.2