From eab5f52d2686712101fe1a839bf845fa1423fce0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 6 Oct 2018 16:50:27 +0100 Subject: [PATCH] add sv c_lwsp unit test --- isa/Makefile | 2 +- isa/macros/simplev/sv_test_macros.h | 4 +- isa/rv64uc/Makefrag.sv | 1 + isa/rv64uc/sv_c_lwsp.S | 64 +++++++++++++++++++++++++++++ 4 files changed, 68 insertions(+), 3 deletions(-) create mode 100644 isa/rv64uc/sv_c_lwsp.S diff --git a/isa/Makefile b/isa/Makefile index 40e57a9..b096935 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -84,7 +84,7 @@ $(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32)) $(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32)) ifeq ($(XLEN),64) $(eval $(call compile_template,rv64ui,-march=rv64g -mabi=lp64)) -$(eval $(call compile_template,rv64uc,-march=rv64g -mabi=lp64)) +$(eval $(call compile_template,rv64uc,-march=rv64gc -mabi=lp64)) $(eval $(call compile_template,rv64um,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64ua,-march=rv64g -mabi=lp64)) $(eval $(call compile_template,rv64uf,-march=rv64g -mabi=lp64)) diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h index 421d0c3..ddf951a 100644 --- a/isa/macros/simplev/sv_test_macros.h +++ b/isa/macros/simplev/sv_test_macros.h @@ -35,8 +35,8 @@ fld reg, offs(x1) #define TEST_SV_IMM( reg, imm ) \ - li x1, imm; \ - bne reg, x1, fail + li t6, imm; \ + bne reg, t6, fail #define TEST_SV_FD( flags, freg, from, offs ) \ fsflags x2, x0; \ diff --git a/isa/rv64uc/Makefrag.sv b/isa/rv64uc/Makefrag.sv index ebd293c..a4a2716 100644 --- a/isa/rv64uc/Makefrag.sv +++ b/isa/rv64uc/Makefrag.sv @@ -5,6 +5,7 @@ rv64uc_sv_tests = \ sv_c_mv \ sv_c_mv_predication \ + sv_c_lwsp \ rv64uc_p_tests = $(addprefix rv64uc-p-, $(rv64uc_sv_tests)) rv64uc_v_tests = $(addprefix rv64uc-v-, $(rv64uc_sv_tests)) diff --git a/isa/rv64uc/sv_c_lwsp.S b/isa/rv64uc/sv_c_lwsp.S new file mode 100644 index 0000000..db3c94f --- /dev/null +++ b/isa/rv64uc/sv_c_lwsp.S @@ -0,0 +1,64 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rvc.S +#----------------------------------------------------------------------------- +# +# Test RVC corner cases. +# + +#include "riscv_test.h" +#include "sv_test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + .align 2 + .option push + .option norvc + + li a2, 0 + li a3, 0 + + SET_SV_MVL(2) + SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1, 0), + SV_REG_CSR(1, 2, 0, 2, 1, 0) ) + SET_SV_VL(2) + + mv a1, sp + la sp, data; + + .option push; + .option rvc; + .align 2; + c.lwsp a2, 0(sp); + #lw a2, 0(sp); + .option pop + + + SET_SV_VL(0) + CLR_SV_CSRS() + SET_SV_MVL(0) + + mv sp, a1 + + TEST_SV_IMM(a2, 1001) + TEST_SV_IMM(a3, 1002) + + .option pop + + RVTEST_PASS # Signal success. +fail: + RVTEST_FAIL + +RVTEST_CODE_END # End of test code. + + .data +data: + .word 1001; + .word 1002; + .word 0x01234567; + +RVTEST_DATA_BEGIN + +RVTEST_DATA_END -- 2.30.2