From f8f43e89f5fc7927cce0387491a8d877c770f536 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 31 Oct 2018 15:03:50 +0000
Subject: [PATCH] add sv fld elwidth test

---
 isa/rv64uf/Makefrag.sv      |  1 +
 isa/rv64uf/sv_fld_elwidth.S | 89 +++++++++++++++++++++++++++++++++++++
 2 files changed, 90 insertions(+)
 create mode 100644 isa/rv64uf/sv_fld_elwidth.S

diff --git a/isa/rv64uf/Makefrag.sv b/isa/rv64uf/Makefrag.sv
index ed9c764..113de68 100644
--- a/isa/rv64uf/Makefrag.sv
+++ b/isa/rv64uf/Makefrag.sv
@@ -4,6 +4,7 @@
 
 rv64uf_sv_tests = \
 	sv_fadd_elwidth \
+	sv_fld_elwidth \
 
 rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sv_tests))
 rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sv_tests))
diff --git a/isa/rv64uf/sv_fld_elwidth.S b/isa/rv64uf/sv_fld_elwidth.S
new file mode 100644
index 0000000..1612065
--- /dev/null
+++ b/isa/rv64uf/sv_fld_elwidth.S
@@ -0,0 +1,89 @@
+#include "riscv_test.h"
+#include "sv_test_macros.h"
+
+RVTEST_RV64UF        # Define TVM used by program.
+
+#define SV_ELWIDTH_TEST( inst, vl, elwidth, wid1, wid2, \
+                         testdata, ans ) \
+                                                        \
+        la x12, testdata ;                              \
+        la x13, (testdata+elwidth);                              \
+        la x14, (testdata+elwidth*2);                              \
+        la x15, (testdata+elwidth*3);                              \
+        la x16, (testdata+elwidth*4);                              \
+        la x17, (testdata+elwidth*5);                              \
+                                                        \
+        li x1, 0xa5a5a5a5a5a5a5a5;                                      \
+        fmv.d.x f28, x1;                                   \
+        fmv.d.x f29, x1;                                   \
+        fmv.d.x f30, x1;                                   \
+                                                        \
+        SET_SV_MVL( vl);                                  \
+        SET_SV_2CSRS( SV_REG_CSR( 1, 12, wid1, 12, 1),        \
+                      SV_REG_CSR( 0, 28, wid2, 28, 1));       \
+        SET_SV_VL( vl );                                   \
+                                                        \
+        inst   f28, 0(x12);                              \
+                                                        \
+        CLR_SV_CSRS();                                  \
+        SET_SV_VL( 1);                                   \
+        SET_SV_MVL( 1);                                  \
+                                                        \
+        TEST_SV_FW(0, f28, ans, 0);                    \
+        TEST_SV_FW(0, f29, ans, 8);                    \
+        TEST_SV_FW(0, f30, ans, 16);                  
+
+# SV test: vector-vector add
+#
+# sets up x3 and x4 with data, sets VL to 2, and carries out
+# an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
+
+# Test code region.
+RVTEST_CODE_BEGIN   # Start of test code.
+
+        SV_ELWIDTH_TEST( fld , 2, 8, SV_W_DFLT, SV_W_DFLT, testdata1, answer1 )
+/*
+        SV_ELWIDTH_TEST(  ld , 3, 8, SV_W_DFLT, SV_W_DFLT, testdata1,
+                0x8979695949392919,  0x8777675747372717,  0x8676665646362616 )
+        SV_ELWIDTH_TEST(  ld , 3, 8, SV_W_16BIT, SV_W_DFLT, testdata1,
+                0x0000000000002919,  0x0000000000004939,  0x0000000000006959 )
+        SV_ELWIDTH_TEST(  ld , 5, 8, SV_W_16BIT, SV_W_32BIT, testdata1,
+                0x0000493900002919,  0xffff897900006959,  0xa5a5a5a500002717 )
+        SV_ELWIDTH_TEST(  ld , 5, 8, SV_W_32BIT, SV_W_16BIT, testdata1,
+                0x6757271769592919,  0xa5a5a5a5a5a52616,  0xa5a5a5a5a5a5a5a5 )
+        SV_ELWIDTH_TEST(  ld , 7, 8, SV_W_16BIT, SV_W_8BIT, testdata1,
+                0xa557371779593919,  0xa5a5a5a5a5a5a5a5,  0xa5a5a5a5a5a5a5a5 )
+        SV_ELWIDTH_TEST(  ld , 11, 8, SV_W_8BIT, SV_W_16BIT, testdata1,
+                0x0049003900290019,  0xff89007900690059,  0xa5a5003700270017 )
+*/
+        RVTEST_PASS           # Signal success.
+fail:
+        RVTEST_FAIL
+RVTEST_CODE_END     # End of test code.
+
+# Input data section.
+# This section is optional, and this data is NOT saved in the output.
+.data
+        .align 3
+testdata1:
+        .dword 0x8979695949392919
+        .dword 0x8777675747372717
+        .dword 0x8676665646362616
+        .dword 0x8272625242322212
+        .dword 0x8171615141312111
+        .dword 0x8373635343332313
+
+answer1:
+        .dword 0x8979695949392919
+        .dword 0x8777675747372717
+        .dword 0xa5a5a5a5a5a5a5a5
+
+# Output data section.
+RVTEST_DATA_BEGIN   # Start of test output data region.
+        .align 3
+result:
+        .dword -1
+        .dword -1
+        .dword -1
+RVTEST_DATA_END     # End of test output data region.
+
-- 
2.30.2