README.txt

   1 # Limitations
   2
   3 * there is no << or >> operator, only <<< and >>> (arithmetic shift)
   4   _Operator("<<", [lhs, rhs]) will generate verilog however simulation
   5   will fail, and value_bits_sign will not correctly recognise it
   6 * it is not possible to declare parameters
   7 * an input of [31:2] is not possible, only a parameter of [N:0]
   8 * tasks are not supported.
   9 * Clock Domains: https://gist.github.com/cr1901/5de5b276fca539b66fe7f4493a5bfe7d