cpu_fetch_stage.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 """
  25
  26 from migen import *
  27 from migen.fhdl import verilog
  28
  29 #from riscvdefs import *
  30 from cpudefs import *
  31
  32
  33 class CPUFetchStage(Module):
  34     def __init__(self):
  35         self.clk = ClockSignal()
  36         self.reset = ResetSignal()
  37         self.reset_vector = Signal(32) #32'hXXXXXXXX; - parameter
  38         self.mtvec = Signal(32) # 32'hXXXXXXXX; - parameter
  39         #output [31:2] memory_interface_fetch_address,
  40         self.memory_interface_fetch_address = Signal(32)
  41         #input [31:0] memory_interface_fetch_data,
  42         self.memory_interface_fetch_data = Signal(32)
  43         self.memory_interface_fetch_valid = Signal()
  44         self.fetch_action = Signal(fetch_action)
  45         self.target_pc = Signal(32)
  46         self.output_pc = Signal(32, reset=self.reset_vector)
  47         self.output_instruction = Signal(32)
  48         self.output_state = Signal(fetch_output_state,
  49                                    reset=FOS.empty)
  50
  51         #self.comb += [
  52         #    self.cd_sys.clk.eq(self.clk),
  53         #    self.cd_sys.rst.eq(self.reset)
  54         #]
  55
  56         fetch_pc = Signal(32, reset=self.reset_vector)
  57
  58         self.sync += If(self.fetch_action != FA.wait,
  59                         self.output_pc.eq(fetch_pc))
  60
  61         self.comb += self.memory_interface_fetch_address.eq(fetch_pc[2:])
  62
  63         #initial output_pc <= self.reset_vector;
  64         #initial output_state <= `FOS.empty;
  65
  66         delayed_instruction = Signal(32, reset=0)
  67         delayed_instruction_valid = Signal(reset=0)
  68
  69         self.sync += delayed_instruction.eq(self.output_instruction)
  70
  71         self.comb += If(delayed_instruction_valid,
  72                     self.output_instruction.eq(delayed_instruction)
  73                 ).Else(
  74                     self.output_instruction.eq(self.memory_interface_fetch_data)
  75                 )
  76
  77         self.sync += delayed_instruction_valid.eq(self.fetch_action ==
  78                                                   FA.wait)
  79
  80         fc = {
  81             FA.ack_trap:
  82                 If(self.memory_interface_fetch_valid,
  83                    [fetch_pc.eq(fetch_pc + 4),
  84                     self.output_state.eq(FOS.valid)]
  85                 ).Else(
  86                    [fetch_pc.eq(self.mtvec),
  87                     self.output_state.eq(FOS.trap)]
  88                 ),
  89             FA.fence:
  90                 [ fetch_pc.eq(self.output_pc + 4),
  91                   self.output_state.eq(FOS.empty)
  92                 ],
  93             FA.jump:
  94                 [ fetch_pc.eq(self.target_pc),
  95                   self.output_state.eq(FOS.empty)
  96                 ],
  97             FA.error_trap:
  98                    [fetch_pc.eq(self.mtvec),
  99                     self.output_state.eq(FOS.empty)
 100                 ],
 101             FA.wait:
 102                    [fetch_pc.eq(fetch_pc),
 103                     self.output_state.eq(FOS.valid)
 104                 ]
 105         }
 106         fc[FA.default] = fc[FA.ack_trap]
 107         fc[FA.noerror_trap] = fc[FA.error_trap]
 108         self.sync += Case(self.fetch_action,
 109                           fc).makedefault(FA.default)
 110
 111 if __name__ == "__main__":
 112     example = CPUFetchStage()
 113     #memory_interface_fetch_address = Signal(32)
 114     print(verilog.convert(example,
 115          { #example.clk,
 116            #example.reset,
 117            example.memory_interface_fetch_address,
 118            example.memory_interface_fetch_data,
 119            example.memory_interface_fetch_valid,
 120            example.fetch_action,
 121            example.target_pc,
 122            example.output_pc,
 123            example.output_instruction,
 124            example.output_state,
 125            example.reset_vector,
 126            example.mtvec
 127             }))