X-Git-Url: https://git.libre-soc.org/?p=rv32.git;a=blobdiff_plain;f=cpu_decoder.py;h=c92fb8898daea15443b74c506b45efc328ed603e;hp=948e10d6a4e1f281d7132c946951f64136bcaa7a;hb=HEAD;hpb=20f36c8d10549a84b19c7563acf5e8a64e16e028 diff --git a/cpu_decoder.py b/cpu_decoder.py index 948e10d..c92fb88 100644 --- a/cpu_decoder.py +++ b/cpu_decoder.py @@ -63,7 +63,7 @@ class CPUDecoder(Module): """ calculate immediate """ ci = {} - no_imm = 0x0 + no_imm = Constant(0x0, 32) # R-type: no immediate for op in [OP.amo, OP.op, OP.op_32, OP.op_fp]: @@ -154,7 +154,7 @@ class CPUDecoder(Module): return self._decode_funct3(DA.jalr, [F3.jalr, ]) def calculate_op_action(self): - """ decode op action + """ decode op action: the arith ops, and, or, add, xor, sr/sl etc. """ c = {} immz = Constant(0, 12) @@ -178,7 +178,7 @@ class CPUDecoder(Module): return Case(self.funct3, c) def calculate_misc_action(self): - """ decode misc mem action + """ decode misc mem action: fence and fence_i """ c = {} immz = Constant(0, 12) @@ -186,14 +186,14 @@ class CPUDecoder(Module): # fence c[F3.fence] = \ If((self.immediate[8:12] == immz) & (self.rs1 == regz) & \ - (self.rd == regz), + (self.rd == regz), self.decode_action.eq(DA.fence) ).Else( self.decode_action.eq(DA.trap_illegal_instruction)) # fence.i c[F3.fence_i] = \ If((self.immediate[0:12] == immz) & (self.rs1 == regz) & \ - (self.rd == regz), + (self.rd == regz), self.decode_action.eq(DA.fence_i) ).Else( self.decode_action.eq(DA.trap_illegal_instruction)) @@ -203,18 +203,18 @@ class CPUDecoder(Module): return Case(self.funct3, c) def calculate_system_action(self): - """ decode system action + """ decode opcode system: ebreak and csrs """ c = {} b1 = Constant(1, 32) regz = Constant(0, 5) # ebreak c[F3.ecall_ebreak] = \ - If((self.immediate != ~b1) | (self.rs1 != regz) | \ - (self.rd != regz), - self.decode_action.eq(DA.trap_illegal_instruction) + If((self.immediate == ~b1) & (self.rs1 == regz) & \ + (self.rd == regz), + self.decode_action.eq(DA.trap_ecall_ebreak) ).Else( - self.decode_action.eq(DA.trap_ecall_ebreak)) + self.decode_action.eq(DA.trap_illegal_instruction)) # csrs for op in [ F3.csrrw, F3.csrrs, F3.csrrc, F3.csrrwi, F3.csrrsi, F3.csrrci]: @@ -232,17 +232,17 @@ class CPUDecoder(Module): (funct7 in the case of arith ops). """ c = {} - c[OP.load] = self.calculate_load_action() + c[OP.load ] = self.calculate_load_action() c[OP.misc_mem] = self.calculate_misc_action() - c[OP.op_imm] = self.calculate_op_action() - c[OP.op] = self.calculate_op_action() - c[OP.lui] = self.decode_action.eq(DA.lui_auipc) - c[OP.auipc] = self.decode_action.eq(DA.lui_auipc) - c[OP.store] = self.calculate_store_action() - c[OP.branch] = self.calculate_branch_action() - c[OP.jalr] = self.calculate_jalr_action() - c[OP.jal] = self.decode_action.eq(DA.jal) - c[OP.system] = self.calculate_system_action() + c[OP.op_imm ] = self.calculate_op_action() + c[OP.op ] = self.calculate_op_action() + c[OP.lui ] = self.decode_action.eq(DA.lui_auipc) + c[OP.auipc ] = self.decode_action.eq(DA.lui_auipc) + c[OP.store ] = self.calculate_store_action() + c[OP.branch ] = self.calculate_branch_action() + c[OP.jalr ] = self.calculate_jalr_action() + c[OP.jal ] = self.decode_action.eq(DA.jal) + c[OP.system ] = self.calculate_system_action() # big batch of unrecognised opcodes: throw trap. for o in [ OP.load_fp, OP.custom_0, OP.op_imm_32,