X-Git-Url: https://git.libre-soc.org/?p=rv32.git;a=blobdiff_plain;f=cpu_fetch_stage.py;h=f3269fb75a9fe890c5e11c9be55c2f7bdcce3e39;hp=820591efa2ab76c723b357712ab51f14aa192c69;hb=2ab5b48210e064bc87131bd6e1451ff89c064931;hpb=164159af1faaa29b3b836bda7fd628cef6904b34

diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py
index 820591e..f3269fb 100644
--- a/cpu_fetch_stage.py
+++ b/cpu_fetch_stage.py
@@ -29,8 +29,6 @@ from migen.fhdl import verilog
 #from riscvdefs import *
 from cpudefs import *
 
-reset_vector = 0x0 #32'hXXXXXXXX;
-mtvec = 0x0 # 32'hXXXXXXXX;
 
 class CPUFetchStage(Module):
     def __init__(self):
@@ -47,6 +45,8 @@ class CPUFetchStage(Module):
         self.output_instruction = Signal(32)
         self.output_state = Signal(fetch_output_state,
                                    reset=fetch_output_state_empty)
+        self.reset_vector = Signal(32) #32'hXXXXXXXX; - parameter
+        self.mtvec = Signal(32) # 32'hXXXXXXXX; - parameter
 
         #self.comb += [
         #    self.cd_sys.clk.eq(self.clk),
@@ -121,4 +121,7 @@ if __name__ == "__main__":
            example.target_pc,
            example.output_pc,
            example.output_instruction,
-           example.output_state }))
+           example.output_state
+           example.reset_vector,
+           example.mtvec
+            }))