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tidyup
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 24 Nov 2018 01:37:16 +0000 (01:37 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 24 Nov 2018 01:37:16 +0000 (01:37 +0000)
cpu_decoder.py patch | blob | history

diff --git a/cpu_decoder.py b/cpu_decoder.py
index 3cb0701ef06370d3e101f930da13b4329226e7ec..c92fb8898daea15443b74c506b45efc328ed603e 100644 (file)
--- a/cpu_decoder.py
+++ b/cpu_decoder.py
@@ -210,7 +210,7 @@ class CPUDecoder(Module):
         regz = Constant(0, 5)
         # ebreak
         c[F3.ecall_ebreak] = \
-            If((self.immediate == ~b1) ^ (self.rs1 == regz) & \
+            If((self.immediate == ~b1) & (self.rs1 == regz) & \
                                          (self.rd == regz),
                 self.decode_action.eq(DA.trap_ecall_ebreak)
             ).Else(