From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 24 Nov 2018 01:37:16 +0000 (+0000)
Subject: tidyup
X-Git-Url: https://git.libre-soc.org/?p=rv32.git;a=commitdiff_plain;h=6e7ea1516de614429e3002b5863f04883530dea7

tidyup
---

diff --git a/cpu_decoder.py b/cpu_decoder.py
index 3cb0701..c92fb88 100644
--- a/cpu_decoder.py
+++ b/cpu_decoder.py
@@ -210,7 +210,7 @@ class CPUDecoder(Module):
         regz = Constant(0, 5)
         # ebreak
         c[F3.ecall_ebreak] = \
-            If((self.immediate == ~b1) ^ (self.rs1 == regz) & \
+            If((self.immediate == ~b1) & (self.rs1 == regz) & \
                                          (self.rd == regz),
                 self.decode_action.eq(DA.trap_ecall_ebreak)
             ).Else(