From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 25 Nov 2018 11:16:16 +0000 (+0000)
Subject: class-ify fetch_action
X-Git-Url: https://git.libre-soc.org/?p=rv32.git;a=commitdiff_plain;h=c714d2845b185d8ce5d54fae0f29e7bf825539c7

class-ify fetch_action
---

diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py
index f3269fb..3eae2ad 100644
--- a/cpu_fetch_stage.py
+++ b/cpu_fetch_stage.py
@@ -34,6 +34,8 @@ class CPUFetchStage(Module):
     def __init__(self):
         self.clk = ClockSignal()
         self.reset = ResetSignal()
+        self.reset_vector = Signal(32) #32'hXXXXXXXX; - parameter
+        self.mtvec = Signal(32) # 32'hXXXXXXXX; - parameter
         #output [31:2] memory_interface_fetch_address,
         self.memory_interface_fetch_address = Signal(32)
         #input [31:0] memory_interface_fetch_data,
@@ -41,26 +43,24 @@ class CPUFetchStage(Module):
         self.memory_interface_fetch_valid = Signal()
         self.fetch_action = Signal(fetch_action)
         self.target_pc = Signal(32)
-        self.output_pc = Signal(32, reset=reset_vector)
+        self.output_pc = Signal(32, reset=self.reset_vector)
         self.output_instruction = Signal(32)
         self.output_state = Signal(fetch_output_state,
                                    reset=fetch_output_state_empty)
-        self.reset_vector = Signal(32) #32'hXXXXXXXX; - parameter
-        self.mtvec = Signal(32) # 32'hXXXXXXXX; - parameter
 
         #self.comb += [
         #    self.cd_sys.clk.eq(self.clk),
         #    self.cd_sys.rst.eq(self.reset)
         #]
 
-        fetch_pc = Signal(32, reset=reset_vector)
+        fetch_pc = Signal(32, reset=self.reset_vector)
 
-        self.sync += If(self.fetch_action != fetch_action_wait,
+        self.sync += If(self.fetch_action != FA.wait,
                         self.output_pc.eq(fetch_pc))
 
         self.comb += self.memory_interface_fetch_address.eq(fetch_pc[2:])
 
-        #initial output_pc <= reset_vector;
+        #initial output_pc <= self.reset_vector;
         #initial output_state <= `fetch_output_state_empty;
 
         delayed_instruction = Signal(32, reset=0)
@@ -75,38 +75,38 @@ class CPUFetchStage(Module):
                 )
 
         self.sync += delayed_instruction_valid.eq(self.fetch_action ==
-                                                  fetch_action_wait)
+                                                  FA.wait)
 
         fc = {
-            fetch_action_ack_trap:
+            FA.ack_trap:
                 If(self.memory_interface_fetch_valid,
                    [fetch_pc.eq(fetch_pc + 4),
                     self.output_state.eq(fetch_output_state_valid)]
                 ).Else(
-                   [fetch_pc.eq(mtvec),
+                   [fetch_pc.eq(self.mtvec),
                     self.output_state.eq(fetch_output_state_trap)]
                 ),
-            fetch_action_fence:
+            FA.fence:
                 [ fetch_pc.eq(self.output_pc + 4),
                   self.output_state.eq(fetch_output_state_empty)
                 ],
-            fetch_action_jump:
+            FA.jump:
                 [ fetch_pc.eq(self.target_pc),
                   self.output_state.eq(fetch_output_state_empty)
                 ],
-            fetch_action_error_trap:
-                   [fetch_pc.eq(mtvec),
+            FA.error_trap:
+                   [fetch_pc.eq(self.mtvec),
                     self.output_state.eq(fetch_output_state_empty)
                 ],
-            fetch_action_wait:
+            FA.wait:
                    [fetch_pc.eq(fetch_pc),
                     self.output_state.eq(fetch_output_state_valid)
                 ]
         }
-        fc[fetch_action_default] = fc[fetch_action_ack_trap]
-        fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap]
+        fc[FA.default] = fc[FA.ack_trap]
+        fc[FA.noerror_trap] = fc[FA.error_trap]
         self.sync += Case(self.fetch_action,
-                          fc).makedefault(fetch_action_default)
+                          fc).makedefault(FA.default)
 
 if __name__ == "__main__":
     example = CPUFetchStage()
@@ -121,7 +121,7 @@ if __name__ == "__main__":
            example.target_pc,
            example.output_pc,
            example.output_instruction,
-           example.output_state
+           example.output_state,
            example.reset_vector,
            example.mtvec
             }))
diff --git a/cpudefs.py b/cpudefs.py
index 4edab97..f4598df 100644
--- a/cpudefs.py
+++ b/cpudefs.py
@@ -26,13 +26,16 @@
 from migen import Constant
 fetch_action = 3
 
-fetch_action_default = Constant(0x0, fetch_action)
-fetch_action_fence = Constant(0x1, fetch_action)
-fetch_action_jump = Constant(0x2, fetch_action)
-fetch_action_wait = Constant(0x3, fetch_action)
-fetch_action_error_trap = Constant(0x4, fetch_action)
-fetch_action_noerror_trap = Constant(0x5, fetch_action)
-fetch_action_ack_trap = Constant(0x6, fetch_action)
+class FA:
+    """ Fetch action constants
+    """
+    default = Constant(0x0, fetch_action)
+    fence = Constant(0x1, fetch_action)
+    jump = Constant(0x2, fetch_action)
+    wait = Constant(0x3, fetch_action)
+    error_trap = Constant(0x4, fetch_action)
+    noerror_trap = Constant(0x5, fetch_action)
+    ack_trap = Constant(0x6, fetch_action)
 
 fetch_output_state = 2