From: Luke Kenneth Casson Leighton Date: Sun, 25 Nov 2018 02:18:20 +0000 (+0000) Subject: small cpu reorg X-Git-Url: https://git.libre-soc.org/?p=rv32.git;a=commitdiff_plain;h=f28e622f6ec07bae947e142ba0aae9cb48493f08 small cpu reorg --- diff --git a/cpu.py b/cpu.py index a975d8e..20da637 100644 --- a/cpu.py +++ b/cpu.py @@ -32,10 +32,32 @@ from migen.fhdl import verilog from riscvdefs import * from cpudefs import * +class MemoryInterface: + fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:] + fetch_data = Signal(32, name="memory_interface_fetch_data") + fetch_valid = Signal(name="memory_interface_fetch_valid") + rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:] + rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask") + rw_read_not_write = Signal(name="memory_interface_rw_read_not_write") + rw_active = Signal(name="memory_interface_rw_active") + rw_data_in = Signal(32, name="memory_interface_rw_data_in") + rw_data_out = Signal(32, name="memory_interface_rw_data_out") + rw_address_valid = Signal(name="memory_interface_rw_address_valid") + rw_wait = Signal(name="memory_interface_rw_wait") + + class CPU(Module): """ """ + def get_ls_misaligned(self, ls, funct3, load_store_address_low_2): + return Case(funct3[:2], + { F3.sb: ls.eq(Constant(0)), + F3.sh: ls.eq(load_store_address_low_2[0] != 0), + F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)), + "default": ls.eq(Constant(1)) + }) + def __init__(self): #self.clk = ClockSignal() #self.reset = ResetSignal() @@ -63,34 +85,24 @@ class CPU(Module): #self.sync += self.registers[0].eq(0) #self.sync += self.registers[1].eq(0) - memory_interface_fetch_address = Signal(32) # XXX [2:] - memory_interface_fetch_data = Signal(32) - memory_interface_fetch_valid = Signal() - memory_interface_rw_address= Signal(32) # XXX [2:] - memory_interface_rw_byte_mask = Signal(4) - memory_interface_rw_read_not_write = Signal() - memory_interface_rw_active = Signal() - memory_interface_rw_data_in = Signal(32) - memory_interface_rw_data_out = Signal(32) - memory_interface_rw_address_valid = Signal() - memory_interface_rw_wait = Signal() - - mi = Instance("cpu_memory_interface", name="memory_instance", + mi = MemoryInterface() + + mii = Instance("cpu_memory_interface", name="memory_instance", p_ram_size = ram_size, p_ram_start = ram_start, i_clk=ClockSignal(), i_rst=ResetSignal(), - i_fetch_address = memory_interface_fetch_address, - o_fetch_data = memory_interface_fetch_data, - o_fetch_valid = memory_interface_fetch_valid, - i_rw_address = memory_interface_rw_address, - i_rw_byte_mask = memory_interface_rw_byte_mask, - i_rw_read_not_write = memory_interface_rw_read_not_write, - i_rw_active = memory_interface_rw_active, - i_rw_data_in = memory_interface_rw_data_in, - o_rw_data_out = memory_interface_rw_data_out, - o_rw_address_valid = memory_interface_rw_address_valid, - o_rw_wait = memory_interface_rw_wait, + i_fetch_address = mi.fetch_address, + o_fetch_data = mi.fetch_data, + o_fetch_valid = mi.fetch_valid, + i_rw_address = mi.rw_address, + i_rw_byte_mask = mi.rw_byte_mask, + i_rw_read_not_write = mi.rw_read_not_write, + i_rw_active = mi.rw_active, + i_rw_data_in = mi.rw_data_in, + o_rw_data_out = mi.rw_data_out, + o_rw_address_valid = mi.rw_address_valid, + o_rw_wait = mi.rw_wait, o_tty_write = self.tty_write, o_tty_write_data = self.tty_write_data, i_tty_write_busy = self.tty_write_busy, @@ -99,7 +111,7 @@ class CPU(Module): o_led_1 = self.led_1, o_led_3 = self.led_3 ) - self.specials += mi + self.specials += mii fetch_act = Signal(fetch_action) fetch_target_pc = Signal(32) @@ -110,9 +122,9 @@ class CPU(Module): fs = Instance("CPUFetchStage", name="fetch_stage", i_clk=ClockSignal(), i_rst=ResetSignal(), - o_memory_interface_fetch_address = memory_interface_fetch_address, - i_memory_interface_fetch_data = memory_interface_fetch_data, - i_memory_interface_fetch_valid = memory_interface_fetch_valid, + o_memory_interface_fetch_address = mi.fetch_address, + i_memory_interface_fetch_data = mi.fetch_data, + i_memory_interface_fetch_valid = mi.fetch_valid, i_fetch_action = fetch_act, i_target_pc = fetch_target_pc, o_output_pc = fetch_output_pc, @@ -169,14 +181,6 @@ class CPU(Module): load_store_address_low_2) self.comb += lsa - def get_ls_misaligned(self, ls, funct3, load_store_address_low_2): - return Case(funct3[:2], - { F3.sb: ls.eq(Constant(0)), - F3.sh: ls.eq(load_store_address_low_2[0] != 0), - F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)), - "default": ls.eq(Constant(1)) - }) - if __name__ == "__main__": example = CPU() @@ -193,26 +197,6 @@ if __name__ == "__main__": """ - function get_load_store_misaligned( - input [2:0] funct3, - input [1:0] load_store_address_low_2 - ); - begin - case(funct3[1:0]) - `funct3_sb: - get_load_store_misaligned = 0; - `funct3_sh: - get_load_store_misaligned = load_store_address_low_2[0] != 0; - `funct3_sw: - get_load_store_misaligned = load_store_address_low_2[1:0] != 0; - default: - get_load_store_misaligned = 1'bX; - endcase - end - endfunction - - wire load_store_misaligned = get_load_store_misaligned(decoder_funct3, load_store_address_low_2); - assign memory_interface_rw_address = load_store_address[31:2]; wire [3:0] unshifted_load_store_byte_mask = {decoder_funct3[1] ? 2'b11 : 2'b00, (decoder_funct3[1] | decoder_funct3[0]) ? 1'b1 : 1'b0, 1'b1};