add Makefile for verilog compilation
[rv32.git] / cpu.py
2018-11-28 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2018-11-28 Luke Kenneth Casso... handle_trap returns values that get manually transferre...
2018-11-27 Luke Kenneth Casso... remove trap_handled, remove w_en
2018-11-27 Luke Kenneth Casso... move handle trap out to separate module, bit messy
2018-11-27 Luke Kenneth Casso... split out cpu_mip to separate module
2018-11-27 Luke Kenneth Casso... split out cpu_mie into separate module
2018-11-27 Luke Kenneth Casso... split out MStatus to separate module
2018-11-27 Luke Kenneth Casso... split cpu loadstore calc out
2018-11-26 Luke Kenneth Casso... move get_fetch_action to separate verilog file
2018-11-26 Luke Kenneth Casso... prepare get_fetch_action for move to separate module
2018-11-26 Luke Kenneth Casso... whoops missed out branch_taken logic from fetch_action
2018-11-26 Luke Kenneth Casso... rename register varnames to regfile
2018-11-26 Luke Kenneth Casso... reorganise cpu regfile, to separate module, with 2R1W...
2018-11-26 Luke Kenneth Casso... complete csrs
2018-11-26 Luke Kenneth Casso... add misa and mstatus csrs
2018-11-26 Luke Kenneth Casso... start adding csrs
2018-11-26 Luke Kenneth Casso... move stuff to MInfo
2018-11-26 Luke Kenneth Casso... split CSR to separate class
2018-11-26 Luke Kenneth Casso... add handle_main
2018-11-26 Luke Kenneth Casso... add counters (TODO)
2018-11-26 Luke Kenneth Casso... add csr_is_valid
2018-11-26 Luke Kenneth Casso... start on csr op valid
2018-11-26 Luke Kenneth Casso... CSR decoding
2018-11-26 Luke Kenneth Casso... add handle_trap
2018-11-26 Luke Kenneth Casso... add handle_trap
2018-11-26 Luke Kenneth Casso... add handle trap
2018-11-26 Luke Kenneth Casso... complete get_fetch_action, move to class Fetch
2018-11-26 Luke Kenneth Casso... start converting get_fetch_action
2018-11-26 Luke Kenneth Casso... create Fetch class
2018-11-26 Luke Kenneth Casso... add get_fetch_action ready for conversion
2018-11-25 Luke Kenneth Casso... add mstatus, mip and vendor/arch/mimpl
2018-11-25 Luke Kenneth Casso... add MISA and MIE
2018-11-25 Luke Kenneth Casso... add more logic and mstatus
2018-11-25 Luke Kenneth Casso... calculate lui_auipc
2018-11-25 Luke Kenneth Casso... minor reorg, add alu
2018-11-25 Luke Kenneth Casso... minor reorg, add alu
2018-11-25 Luke Kenneth Casso... convert loaded value
2018-11-25 Luke Kenneth Casso... load value
2018-11-25 Luke Kenneth Casso... more cpu logic
2018-11-25 Luke Kenneth Casso... small cpu reorg
2018-11-25 Luke Kenneth Casso... add load/store misaligned
2018-11-25 Luke Kenneth Casso... add CPU decoder instance
2018-11-25 Luke Kenneth Casso... add cpuFetchStage instance
2018-11-25 Luke Kenneth Casso... adding call out to cpu_memory_interface verilog module...
2018-11-24 Luke Kenneth Casso... stub cpu.py