From 84762ebcde7d4dc6493571f7337637e747139876 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 22 Nov 2018 19:12:39 +0000 Subject: [PATCH] cleanup, use sync instead of comb where appropriate --- cpu_fetch_stage.py | 36 +++++++++++++++++++++++++----------- 1 file changed, 25 insertions(+), 11 deletions(-) diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py index 216aa5e..3d25d35 100644 --- a/cpu_fetch_stage.py +++ b/cpu_fetch_stage.py @@ -41,11 +41,12 @@ class CPUFetchStage(Module): #input [31:0] memory_interface_fetch_data, self.memory_interface_fetch_data = Signal(32) self.memory_interface_fetch_valid = Signal() - input `fetch_action fetch_action, - input [31:0] target_pc, + self.fetch_action = Signal(fetch_action) + self.target_pc = Signal(32) self.output_pc = Signal(32, reset=reset_vector) self.output_instruction = Signal(32) - output reg `fetch_output_state output_state + self.output_state = Signal(fetch_output_state, + reset=fetch_output_state_empty) self.comb += [ self.cd_sys.clk.eq(self.clk), @@ -54,7 +55,11 @@ class CPUFetchStage(Module): fetch_pc = Signal(32, reset=reset_vector) - self.sync += output_pc.eq((fetch_action == `fetch_action_wait) ? output_pc : fetch_pc); + self.sync += If(fetch_action != fetch_action_wait, + output_pc.eq(fetch_pc)). + Else( output_pc.eq(output_pc)) # hmmm... + #self.sync += output_pc.eq((fetch_action == `fetch_action_wait) ? + # output_pc : fetch_pc); memory_interface_fetch_address = fetch_pc[2:] @@ -67,9 +72,14 @@ class CPUFetchStage(Module): self.sync += delayed_instruction.eq(output_instruction) self.sync += output_state.eq(fetch_output_state_empty) - self.comb += output_instruction.eq(delayed_instruction_valid ? delayed_instruction : memory_interface_fetch_data) + self.comb += If(delayed_instruction_valid, + output_instruction.eq(delayed_instruction) + ).Else( + output_instruction.eq(memory_interface_fetch_data) + ) - self.sync += delayed_instruction_valid.eq(fetch_action == `fetch_action_wait) + self.sync += delayed_instruction_valid.eq(fetch_action == + fetch_action_wait) fc = { fetch_action_ack_trap: @@ -82,18 +92,22 @@ class CPUFetchStage(Module): ), fetch_action_fence: [ fetch_pc.eq(output_pc + 4), - output_state.eq(fetch_output_state_empty)], + output_state.eq(fetch_output_state_empty) + ], fetch_action_jump: [ fetch_pc.eq(target_pc), - output_state.eq(fetch_output_state_empty)], + output_state.eq(fetch_output_state_empty) + ], fetch_action_error_trap, [fetch_pc.eq(mtvec), - output_state.eq(fetch_output_state_empty)], + output_state.eq(fetch_output_state_empty) + ], fetch_action_wait: [fetch_pc.eq(fetch_pc), - output_state.eq(fetch_output_state_valid)] + output_state.eq(fetch_output_state_valid) + ] } fc[fetch_action_default] = fc[fetch_action_ack_trap] fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap] - self.comb += Case(fetch_action, fc).makedefault(fetch_action_default) + self.sync += Case(fetch_action, fc).makedefault(fetch_action_default) -- 2.30.2