From 9d77f07c15f97cbeb63f8d3217bf1384f66a57bb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 22 Nov 2018 00:21:59 +0000 Subject: [PATCH] reorg case statement --- cpu_fetch_stage.py | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py index f35e68c..216aa5e 100644 --- a/cpu_fetch_stage.py +++ b/cpu_fetch_stage.py @@ -71,28 +71,29 @@ class CPUFetchStage(Module): self.sync += delayed_instruction_valid.eq(fetch_action == `fetch_action_wait) - fc = {} - self.comb += Case(fetch_action, fc) - fc[fetch_action_ack_trap] = + fc = { + fetch_action_ack_trap: If(memory_interface_fetch_valid, [fetch_pc.eq(fetch_pc + 4), output_state.eq(fetch_output_state_valid)] ).Else( [fetch_pc.eq(mtvec), output_state.eq(fetch_output_state_trap)] - ) - fc[fetch_action_default] = fc[fetch_action_ack_trap] - fc[fetch_action_fence] = + ), + fetch_action_fence: [ fetch_pc.eq(output_pc + 4), - output_state.eq(fetch_output_state_empty)] - fc[fetch_action_jump] = + output_state.eq(fetch_output_state_empty)], + fetch_action_jump: [ fetch_pc.eq(target_pc), - output_state.eq(fetch_output_state_empty)] - fc[fetch_action_error_trap] = + output_state.eq(fetch_output_state_empty)], + fetch_action_error_trap, [fetch_pc.eq(mtvec), - output_state.eq(fetch_output_state_empty)] - fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap] - fc[fetch_action_wait] = + output_state.eq(fetch_output_state_empty)], + fetch_action_wait: [fetch_pc.eq(fetch_pc), output_state.eq(fetch_output_state_valid)] + } + fc[fetch_action_default] = fc[fetch_action_ack_trap] + fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap] + self.comb += Case(fetch_action, fc).makedefault(fetch_action_default) -- 2.30.2