> Data Read phase is on posedge and Data write is on negdege
-- send the received arid and bid's so that DMA can identify. duplicate instead of extend
*/
+ import GetPut::*;
import TriState::*;
import ConcatReg ::*;
import Semi_FIFOF :: *;
/*(* always_ready, result="io3_sdio_ctrl" *) */
method Bit#(9) io3_sdio_ctrl;
/*(* always_ready, result="io_enable" *)*/
- interface Get#(Bit#(4)) io_outen;
+ interface Get#(Bit#(4)) io_out_en;
/*(* always_ready, always_enabled *) */
//method Action io_i ((* port="io_i" *) Bit#(4) io_in); // in
interface Put#(Bit#(4)) io_in;
endinterface;
interface ncs_o = interface Get
method ActionValue#(Bit#(1)) get;
- return ncs
+ return ncs;
endmethod
endinterface;
endinterface