import BUtils ::*;
import AXI4_Lite_Types::*;
- interface Ifc_rgbttl_dummy()
+ interface Ifc_rgbttl_dummy;
interface AXI4_Lite_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
method Bit#(1) de;
method Bit#(1) ck;
endinterface
(*synthesize*)
- module mkrgbttl_dummy(Ifc_rgbttl_dummy)
+ module mkrgbttl_dummy(Ifc_rgbttl_dummy);
AXI4_Lite_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
s_xactor<-mkAXI4_Lite_Slave_Xactor();
- let v_buswidth = valueOf(v_buswidth);
Reg#(Bit#(1)) rg_de <- mkReg(0);
Reg#(Bit#(1)) rg_ck <- mkReg(0);
Reg#(Bit#(1)) rg_vs <- mkReg(0);
Reg#(Bit#(1)) rg_hs <- mkReg(0);
- Reg#(Bit#(`RGBTTL_WIDTH)) rg_data;
- for(Integer i = 0; i < `RGBTTL_WIDTH;i=i+1) begin
- rg_data[i] <- mkReg(0);
- end
+ Reg#(Bit#(`RGBTTL_WIDTH)) rg_data <- mkReg(0);
method de = rg_de;
method ck = rg_ck;