adding master and slave interface to rgbtll

[shakti-peripherals.git] / src / peripherals / rgbttl / rgbttl_dummy.bsv

diff --git a/src/peripherals/rgbttl/rgbttl_dummy.bsv b/src/peripherals/rgbttl/rgbttl_dummy.bsv
index 19dfd1efc5bee6c277fcd87de51c90b0de23a669..a52d5e7db27f36ee367a652d6a0ea0c6dbe3284f 100644 (file)
--- a/src/peripherals/rgbttl/rgbttl_dummy.bsv
+++ b/src/peripherals/rgbttl/rgbttl_dummy.bsv
@@ -29,42 +29,66 @@ Details:
 --------------------------------------------------------------------------------------------------
 */
 package rgbttl_dummy;
+  `define RGBTTL_WIDTH 18
   `include "instance_defines.bsv"
-  import ClockDiv::*;
-  import ConcatReg::*;
-  import Semi_FIFOF::*;
+  import GetPut::*;
   import BUtils ::*;
-  import AXI4_Lite_Types::*;
+  import AXI4_Types::*;
 
-  interface Ifc_rgbttl_dummy#(numeric type buswidth);
-         interface AXI4_Lite_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
-    method  Bit#(1) de; 
-    method  Bit#(1) ck;
-    method  Bit#(1) vs;
-    method  Bit#(1) hs;
-    method  Bit#(buswidth) data;
+  interface Ifc_rgbttl_dummy;
+           interface AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
+           interface AXI4_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
+      interface Get#(Bit#(1)) de;
+      interface Get#(Bit#(1)) ck;
+      interface Get#(Bit#(1)) vs;
+      interface Get#(Bit#(1)) hs;
+      interface Get#(Bit#(`RGBTTL_WIDTH)) data_out;
   endinterface
 
   (*synthesize*)
-  module mkrgbttl_dummy(Ifc_rgbttl_dummy#(buswidth))
-               AXI4_Lite_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
-                            s_xactor<-mkAXI4_Lite_Slave_Xactor();
-      let v_buswidth = valueOf(v_buswidth);
+  module mkrgbttl_dummy(Ifc_rgbttl_dummy);
+               AXI4_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
+                            s_xactor<-mkAXI4_Slave_Xactor();
+               AXI4_Master_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
+                            m_xactor<-mkAXI4_Master_Xactor();
 
       Reg#(Bit#(1)) rg_de <- mkReg(0);
       Reg#(Bit#(1)) rg_ck <- mkReg(0);
       Reg#(Bit#(1)) rg_vs <- mkReg(0);
       Reg#(Bit#(1)) rg_hs <- mkReg(0);
-      Reg#(Bit#(v_buswidth)) rg_data;
-      for(Integer i = 0; i < v_no_of_ir_pins;i=i+1) begin
-        rg_data[i] <- mkReg(0);
-      end
+      Reg#(Bit#(`RGBTTL_WIDTH)) rg_data <- mkReg(0);
 
-    method  de = rg_de; 
-    method  ck = rg_ck;
-    method  vs = rg_vs;
-    method  hs = rg_hs;
-    method  data = rg_data;
-    interface slave=s_xactor.axi_side;
+      interface de = interface Get
+        method ActionValue#(Bit#(1)) get;
+          return rg_de;
+        endmethod
+      endinterface;
+
+      interface ck = interface Get
+        method ActionValue#(Bit#(1)) get;
+          return rg_ck;
+        endmethod
+      endinterface;
+
+      interface vs = interface Get
+        method ActionValue#(Bit#(1)) get;
+          return rg_vs;
+        endmethod
+      endinterface;
+
+      interface hs = interface Get
+        method ActionValue#(Bit#(1)) get;
+          return rg_hs;
+        endmethod
+      endinterface;
+
+      interface data_out = interface Get
+        method ActionValue#(Bit#(`RGBTTL_WIDTH)) get;
+          return rg_data;
+        endmethod
+      endinterface;
+
+      interface slave=s_xactor.axi_side;
+      interface master=m_xactor.axi_side;
   endmodule
 endpackage