From 8b0ce8a367a9d8aaec8a0b7804185544b18cbcb0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 26 Jul 2018 12:49:47 +0100 Subject: [PATCH] start converting flexbus to get/put --- src/peripherals/flexbus/FlexBus_Types.bsv | 159 +++++++++++++--------- 1 file changed, 91 insertions(+), 68 deletions(-) diff --git a/src/peripherals/flexbus/FlexBus_Types.bsv b/src/peripherals/flexbus/FlexBus_Types.bsv index 9211640..5a7055f 100644 --- a/src/peripherals/flexbus/FlexBus_Types.bsv +++ b/src/peripherals/flexbus/FlexBus_Types.bsv @@ -37,6 +37,7 @@ mkAXI4_Slave_to_FlexBus_Master_Xactor; import Vector :: *; import FIFOF :: *; +import GetPut :: *; import SpecialFIFOs:: *; import Connectable :: *; import ConfigReg :: *; @@ -61,26 +62,25 @@ import Memory_AXI4 :: *; // The (*..*) attributes ensure that when bsc compiles this to Verilog, // we get exactly the signals specified in the FlexBus spec. +(* always_ready *) interface FlexBus_Master_IFC; // FlexBus External Signals // AD inout bus separate for now in BSV - (* always_ready, result="AD" *) method Bit #(32) m_AD; // out + (* result="AD" *) interface Get#(Bit#(32)) m_AD; // out + interface Put#(Bit#(32) m_din; // in - //(* always_ready, always_enabled *) method Action m_din ((* port="din" *) Bit #(32) din); // in - method Action m_din ((* port="din" *) Bit #(32) din); // in + (* result="R_Wn" *) interface Get#(Bit#(1)) m_R_Wn; // out + (* result="R_Wn" *) interface Get#(Bit#(1)) m_R_Wn; // out + (* result="TSIZ" *) interface Get#(Bit #(2) m_TSIZ; // out - (* always_ready, result="R_Wn" *) method Bit #(1) m_R_Wn; // out - (* always_ready, result="TSIZ" *) method Bit #(2) m_TSIZ; // out + (* result="FBCSn" *) interface Get#(Bit#(6)) m_FBCSn; // out + (* result="BEn_BWEn" *) interface Get#(Bit#(4)) m_BE_BWEn; // out + (* result="TBSTn" *) interface Get#(Bit#(1)) m_TBSTn; // out + (* result="OEn" *) interface Get#(Bit#(1)) m_OEn; // out - (* always_ready, result="FBCSn" *) method Bit #(6) m_FBCSn; // out - (* always_ready, result="BEn_BWEn" *) method Bit #(4) m_BE_BWEn; // out - (* always_ready, result="TBSTn" *) method Bit #(1) m_TBSTn; // out - (* always_ready, result="OEn" *) method Bit #(1) m_OEn; // out - - (* always_ready, result="ALE" *) method Bit #(1) m_ALE; // out - //(* always_ready, always_enabled *) method Action m_TAn ((* port="TAn" *) Bit #(1) tAn); // in - method Action m_TAn ((* port="TAn" *) Bit #(1) tAn); // in + (* result="ALE" *) interface Get#(Bit#(1)) m_ALE; // out + interface Put#(Bit#(1) tAn; // in endinterface: FlexBus_Master_IFC @@ -93,7 +93,7 @@ endinterface: FlexBus_Register_Input_IFC interface FlexBus_Register_Output_IFC; (* always_ready, always_enabled *) method Bit#(6) m_FBCSn(); (* always_ready, always_enabled *) method Bit#(6) m_SWS(); - (* always_ready, always_enabled *) method Bit#(1) m_SWS_EN(); + (* always_ready, always_enabled *) method Bit#(1) m_SWS_EN(); (* always_ready, always_enabled *) method Bit#(2) m_ASET(); (* always_ready, always_enabled *) method Bit#(2) m_RDAH(); (* always_ready, always_enabled *) method Bit#(2) m_WRAH(); @@ -114,24 +114,23 @@ endinterface: FlexBus_Register_IFC // These are the signal-level interfaces for an AXI4-Lite slave. // The (*..*) attributes ensure that when bsc compiles this to Verilog, // we get exactly the signals specified in the ARM spec. - +(* always_ready, always_enabled *) interface FlexBus_Slave_IFC ; - (* always_ready, always_enabled *) method Action m_AD ( (* port="AD" *) Bit #(32) i_AD); // in - - - (* always_ready, always_enabled *) method Action m_ALE ( (* port="ALE" *) Bit #(1) i_ALE); // in - - (* always_ready, always_enabled *) method Action m_R_Wn ( (* port="R_Wn" *) Bit #(1) i_R_Wn); // in - (* always_ready, always_enabled *) method Action m_TSIZ ( (* port="TSIZ" *) Bit #(2) i_TSIZ); // in - - (* always_ready, always_enabled *) method Action m_FBCSn ( (* port="FBCSn" *) Bit #(6) i_FBCSn); // in - (* always_ready, always_enabled *) method Action m_BE_BWEn ( (* port="BE_BWEn" *) Bit #(4) i_BE_BWEn); // in - (* always_ready, always_enabled *) method Action m_TBSTn ( (* port="TBSTn" *) Bit #(1) i_TBSTn); // in - (* always_ready, always_enabled *) method Action m_OEn ( (* port="OEn" *) Bit #(1) i_OEn); // in - - (* always_ready, result="din" *) method Bit #(32) m_din; // out - (* always_ready, result="TAn" *) method Bit #(1) m_TAn; // out + (* result="AD" *) interface Put#(Bit#(32)) m_AD; // out + interface Get#(Bit#(32) m_din; // in + + (* result="R_Wn" *) interface Put#(Bit#(1)) m_R_Wn; // out + (* result="R_Wn" *) interface Put#(Bit#(1)) m_R_Wn; // out + (* result="TSIZ" *) interface Put#(Bit #(2) m_TSIZ; // out + + (* result="FBCSn" *) interface Put#(Bit#(6)) m_FBCSn; // out + (* result="BEn_BWEn" *) interface Put#(Bit#(4)) m_BE_BWEn; // out + (* result="TBSTn" *) interface Put#(Bit#(1)) m_TBSTn; // out + (* result="OEn" *) interface Put#(Bit#(1)) m_OEn; // out + + (* result="ALE" *) interface Put#(Bit#(1)) m_ALE; // out + interface Get#(Bit#(1) tAn; // in endinterface: FlexBus_Slave_IFC @@ -1047,45 +1046,69 @@ module mkAXI4_Slave_to_FlexBus_Master_Xactor interface flexbus_side = interface FlexBus_Master_IFC; //interface io_AD_master = tri_AD_out.io; - method Action m_TAn (Bit #(1) tAn) if(c_TAn[0] matches tagged Invalid); - c_TAn[0] <= tagged Valid tAn; - endmethod - method Action m_din ( Bit#(32) din )if(c_din[0] matches tagged Invalid); - c_din[0] <= tagged Valid din; - endmethod - method Bit #(32) m_AD; - return r_AD; - endmethod - - - method Bit #(1) m_R_Wn; // out - return r_R_Wn; - endmethod - method Bit #(2) m_TSIZ; // out - return r_TSIZ; - endmethod - - - - method Bit #(6) m_FBCSn; // out - return r_FBCSn; - endmethod - method Bit #(4) m_BE_BWEn; // out - return r_BE_BWEn; - endmethod - method Bit #(1) m_TBSTn; // out - return r_TBSTn; - endmethod - method Bit #(1) m_OEn; // out - return r_OEn; - endmethod - - method Bit #(1) m_ALE; // out - return r_ALE; - endmethod - //endinterface; + interface c_TAn = interface Put + method Action put(Bit#(1) in) if(c_TAn[0] matches tagged Invalid); + c_TAn[0] <= tagged Valid in; + endmethod + endinterface; - endinterface; + interface m_din = interface Put + method Action put(Bit#(32) in) if(c_din[0] matches tagged Invalid); + c_din[0] <= tagged Valid in; + endmethod + endinterface; + + interface m_AD = interface Get + method ActionValue#(Bit#(32)) get; + return r_AD; + endmethod + endinterface; + + interface m_R_Wn = interface Get + method ActionValue#(Bit#(1)) get; + return r_R_Wn; + endmethod + endinterface; + + interface m_TSIZ = interface Get + method ActionValue#(Bit#(2)) get; + return r_TSIZ; + endmethod + endinterface; + + interface m_FBCSn = interface Get + method ActionValue#(Bit#(6)) get; + return r_FBCSn; + endmethod + endinterface; + + interface m_BE_BWEn = interface Get + method ActionValue#(Bit#(4)) get; + return r_BE_BWEn; + endmethod + endinterface; + + interface m_TBSTn = interface Get + method ActionValue#(Bit#(1)) get; + return r_TBSTn; + endmethod + endinterface; + + interface m_OEn = interface Get + method ActionValue#(Bit#(1)) get; + return r_OEn; + endmethod + endinterface; + + interface m_ALE = interface Get + method ActionValue#(Bit#(1)) get; + return r_ALE; + endmethod + endinterface; + + //endinterface; + +endinterface; endmodule: mkAXI4_Slave_to_FlexBus_Master_Xactor -- 2.30.2