src/main/scala/devices/i2c/I2CPins.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.i2c
   3
   4 import Chisel._
   5 import chisel3.experimental.{withClockAndReset}
   6 import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
   7 import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
   8
   9 class I2CSignals[T <: Data](private val pingen: () => T) extends Bundle {
  10   val scl: T = pingen()
  11   val sda: T = pingen()
  12 }
  13
  14 class I2CPins[T <: Pin](pingen: () => T) extends I2CSignals[T](pingen)
  15
  16 object I2CPinsFromPort {
  17
  18   def apply[T <: Pin](pins: I2CSignals[T], i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
  19     withClockAndReset(clock, reset) {
  20       pins.scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
  21       pins.scl.o.oe := i2c.scl.oe
  22       i2c.scl.in := SyncResetSynchronizerShiftReg(pins.scl.i.ival, syncStages, init = Bool(true),
  23         name = Some("i2c_scl_sync"))
  24
  25       pins.sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
  26       pins.sda.o.oe := i2c.sda.oe
  27       i2c.sda.in := SyncResetSynchronizerShiftReg(pins.sda.i.ival, syncStages, init = Bool(true),
  28         name = Some("i2c_sda_sync"))
  29     }
  30   }
  31 }