src/main/scala/devices/i2c/I2CPins.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.i2c
   3
   4 import Chisel._
   5 import chisel3.experimental.{withClockAndReset}
   6 import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
   7 import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
   8
   9 class I2CSignals[T <: Data](pingen: () => T) extends Bundle {
  10
  11   val scl: T = pingen()
  12   val sda: T = pingen()
  13
  14   override def cloneType: this.type =
  15     this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
  16 }
  17
  18 class I2CPins[T <: Pin](pingen: () => T) extends I2CSignals[T](pingen) {
  19   override def cloneType: this.type =
  20     this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
  21
  22   def fromPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
  23     withClockAndReset(clock, reset) {
  24       scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
  25       scl.o.oe := i2c.scl.oe
  26       i2c.scl.in := SyncResetSynchronizerShiftReg(scl.i.ival, syncStages, init = Bool(true),
  27         name = Some("i2c_scl_sync"))
  28
  29       sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
  30       sda.o.oe := i2c.sda.oe
  31       i2c.sda.in := SyncResetSynchronizerShiftReg(sda.i.ival, syncStages, init = Bool(true),
  32         name = Some("i2c_sda_sync"))
  33     }
  34   }
  35 }