src/main/scala/devices/jtag/JTAGPins.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.jtag
   3
   4 import Chisel._
   5
   6 // ------------------------------------------------------------
   7 // SPI, UART, etc are with their respective packages,
   8 // JTAG doesn't really correspond directly to a device, but it does
   9 // define pins as those devices do.
  10 // ------------------------------------------------------------
  11
  12 import freechips.rocketchip.config._
  13 import freechips.rocketchip.jtag.{JTAGIO}
  14 import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
  15
  16 class JTAGPins[T <: Pin](pingen: () => T, hasTRSTn: Boolean = true) extends Bundle {
  17
  18   val TCK         = pingen()
  19   val TMS         = pingen()
  20   val TDI         = pingen()
  21   val TDO        = pingen()
  22   val TRSTn = if (hasTRSTn) Option(pingen()) else None
  23
  24   def fromPort(jtag: JTAGIO): Unit = {
  25     jtag.TCK  := TCK.inputPin (pue = Bool(true)).asClock
  26     jtag.TMS  := TMS.inputPin (pue = Bool(true))
  27     jtag.TDI  := TDI.inputPin(pue = Bool(true))
  28     jtag.TRSTn.foreach{t => t := TRSTn.get.inputPin(pue = Bool(true))}
  29
  30     TDO.outputPin(jtag.TDO.data)
  31     TDO.o.oe := jtag.TDO.driven
  32   }
  33 }